WikiChip Fuse

I believe this report by WikiChip from IEDM 2022 is an accurate summary of the situation: > While there were a great number of interesting papers from both academia and industry, it was the one by TSMC that brought frighteningly bad news: whereas logic is still scaling more-or-less along the historical trendline, SRAM scaling appears to have completely collapsed. https://fuse.wikichip.org/news/7343/iedm-2022-did-we-just-witness-the-…

We discussed a different project from the same source a little over a month ago[1]. Yes, they are making transistors out of plastic[2]. ”We coat everything on that, then peel it off and reuse the glass a carriers which means we can use silicon equipment.” That they manage to get this to work at all is amazing. I view this as a technology demonstrator more than anything else. It looks like there's a pent up demand for low end processing that this might fill. Still no comment about this from Sam Zeloof[3] 8) [1] - https://fuse.wikichip.org/news/6648/reincarnating-the-6502-using-flexi… [2] - https://www.eenewseurope.com/en/first-300mm-fab-for-the-uk/ [3] - https://twitter.com/szeloof

Apparently Japan withdrew funding from the company developing this[1]. Hopefully another company can pick this up eventually to see if its worth using. iirc the fraud was financial and the tech was legit, but please correct me if I'm wrong. 1. https://fuse.wikichip.org/news/1204/pezys-future-is-uncertain-as-japan…

> the CPU won't look ahead 200 instructions to find more parallel stuff to execute CPUs do: > Intel increased the reorder buffer by over 50% from 224 entries in Skylake to 352 entries in Sunny Cove. Likewise, the amount of inflight loads and stores has been increased by over 50% to 200 memory operations inflight. https://fuse.wikichip.org/news/2371/intel-sunny-cove-core-to-deliver-a…

Great points. I'd like to add that IBM's latest mainframe is the z14 (z14 seems to be the name of both the CPU and the mainframe) and it's pretty interesting: https://fuse.wikichip.org/news/941/isscc-2018-the-ibm-z14-microprocess… (No affiliation with IBM)

Up until now Foveros has only allowed chips to be fully stacked on top of each other. With Foveros Direct, supposely coming in Meteor Lake[1], stacked chips might also having connections from elsewhere (via the base/substrate/interposer/eimb). Previously stacked chips had to have their connectivity & power mediated through another chip, but now stacked chips are supposedly going to be able to have some of their own connectivity as well. This should enable much more interesting stacks. Intel's process technology might have struggled for a while, but Intel has been developing absolutely top notch ways to combine chips together. It's less a story about multi-chip, but Intel's really been figuring out how to mix and match in other ways too: the E-cores they ship everywhere are finally an Atom good enough for everyone & that do great. I feel like they've had a lot of really good projects. Not sure how important this is, but it'll be interesting to see if they can make MCM & this all work for really low power. Intel Galileo showed huge promise as a smart device/application-processor chip, many years back. Lakefield (much bigger, more recent, mobile class) had a lot of promise as an ultraportable chip, but wasn't noticeably enough lower power at it's slower speed, but was so promising & so so small footprint (still better than a Snapdragon!). It's hard to picture the chiplet world being good for edge, good for low power: it feels more like a bigger play. But with all the mix &…

FWIW, the active channel volume is much more than a dozen atoms in a modern FinFET process. For a ~5nm process, there might be only a few dozen atoms across the width of the fin, but the other dimensions are much larger, for a total of probably somewhere around hundreds of thousands of atoms per channel. see e.g. https://fuse.wikichip.org/news/2408/tsmc-7nm-hd-and-hp-cells-2nd-gen-7… and other wikichip articles for some dimension info. but regardless, modern semiconductor manufacturing processes are incredible. the much-too-brief summary is that they shine very precise patterns of light on the silicon using very high frequency light to activate photoresist, and then etching away the silicon that isn't protected by the photoresist. this doesn't actually produce features as small as the fins, so there are a lot of tricky techniques, like doing this patterning + etching once, then growing a layer of some other material on top, then etching again to leave only the very narrow sidewalls that grew around the original feature, then etching again using the sidewalls as the pattern. https://en.wikipedia.org/wiki/Spacer_patterning it really is amazing - reliably writing tiny structures on stones with light.

https://fuse.wikichip.org/news/6853/arm-introduces-the-cortex-a715/ It was one of the biggest features of A715 going by ARM’s slides.

That's way too wasteful. Take a look at https://fuse.wikichip.org/news/3010/a-look-at-cerebras-wafer-scale-eng… and specifically the diagram https://fuse.wikichip.org/wp-content/uploads/2019/11/hc31-cerebras-mem… The fabric can effectively route signals diagonally to work around an individual defective core, with a displacement of one position for cores in the same row from that defect over to the nearest spare core. That's how they get away with a claimed "1–1.5%" of spare cores.

I mostly agree, but if TSMC and Samsung are "lying" about nanometers... what is Intel supposed to do about that? Just keep punching themselves in the face by underselling their processes? Also see https://fuse.wikichip.org/wp-content/uploads/2022/12/hp-density-14nm-5…

3 hierarchies of featuresets in which each implies all prior features are available seems better than the current situation: https://fuse.wikichip.org/wp-content/uploads/2019/12/avx512_uarchs.png

Many interesting chips escape Wikipedia's gaze. For instance, there was a very interesting x86, Zen-like CPU from Centaur with an onboard AI accelerator that is basically undocumented on Wikipedia: https://fuse.wikichip.org/news/3256/centaur-new-x86-server-processor-p… https://fuse.wikichip.org/news/3099/centaur-unveils-its-new-server-cla…

Only an Apple engineer could answer this fully but here are some of my ideas as to why this hasn't been done yet: -They still support playback on devices with no TEE. Kinda defeats the point of implementing it until this is the case. - They are wary of moving more functionality into their TEE as it increases the attack surface. - If the platform is already "attested" and locked down as it is the case today, moving the playback to the TEE provides only a little bit of extra security. - They are banking on the ARM Realm Management Extension[0] coming to their chips. This would be more of a "catch all" solution to fuck over the owners of their machines in new and exciting ways. [0]: https://fuse.wikichip.org/news/5699/arm-introduces-its-confidential-co…

> Apple has booked nearly 90% of chip supplier TSMC's first-generation 3-nanometer process capacity this year No surprise, the N3B ("first gen") process has bad economics and poor yields. Everyone else is waiting for N3E, which is pretty different to N3B. See: https://www.semianalysis.com/p/tsmcs-3nm-conundrum-does-it-even https://fuse.wikichip.org/news/7048/n3e-replaces-n3-comes-in-many-flav…

This article about Intel candy canes and unicorns and rainbows looks like simply a large hit of cocaine to keep their bloodied investors hopes' up! To quote Newt from alien 2, "Ripley, it won't make a difference!" because SRAM is NOT scaling down! https://fuse.wikichip.org/news/7343/iedm-2022-did-we-just-witness-the-…

Here is a link to the WikiChip article mentioned by the XDA article. It's a bit more technical and has some pretty nice graphs showing information about the different densities of SRAM at each different node/fab size. https://fuse.wikichip.org/news/7343/iedm-2022-did-we-just-witness-the-…

IBM has been doing this for a long time. Eg here's one mainframe CPU with 960 MB of L4: https://fuse.wikichip.org/news/3383/ibm-doubles-its-14nm-edram-density… (They also have DRAM in other levels of cache hierarchy except L1, with L2 running at 5+ GHz)

> One thing that Intel and AMD do better than any other player in the industry is branch prediction. An absolutely stupifying amount of die area is dedicated to it on x86. Zen in particular combines an L1 perceptron and L2 TAGE[0] predictor[1]. TAGE in particular requires an immense amount of silicon, but it has something like 99.7% prediction accuracy, which is... crazy. The perceptron predictor is almost as good: 99.5%. I wrote a software TAGE predictor, but too bad it didn't perform as well as predicted (heh) by the authors of the paper. [0]: https://doi.org/10.1145/2155620.2155635 [1]: https://fuse.wikichip.org/news/2458/a-look-at-the-amd-zen-2-core/

I don't think so. The new ISA that is in the SPR is mostly about deep learning: it supports int8 and bfloat16 (https://fuse.wikichip.org/news/3600/the-x86-advanced-matrix-extension-… You can emulate higher precision using bfloat16 (https://arxiv.org/abs/1904.06376), but I have not seen this used in the wild.

https://fuse.wikichip.org/news/3010/a-look-at-cerebras-wafer-scale-eng… Power fed vertically. Not sure it's BPR specifically, but they do mention ~50% efficiency improvement in the PDN so it's comparable.

AMD Zen 1 had a neural net branch predictor for real. But Zen2 / Zen3 don't seem to have this idea referenced anywhere. I can only imagine that AMD managed to beat their neural-net branch predictor with some boring methodology. EDIT: https://fuse.wikichip.org/news/2458/a-look-at-the-amd-zen-2-core/ Wikichip has done an article on it.

I got L1 being SRAM from here https://fuse.wikichip.org/news/3383/ibm-doubles-its-14nm-edram-density…

Intel's 14nm process is, in terms of dimensions, closer to TSMC's 10nm, and their 10nm is only slightly larger than TSMC's 7nm: https://fuse.wikichip.org/wp-content/uploads/2018/02/iedm-2017-intel-1… That being said they really need to step up their game or else they'll be bleeding market share for years to come.

Intel recently disclosed an ISA extension for matrix operations called Advanced Matrix Extensions (AMX). It should appear in Sapphire Rapids. https://fuse.wikichip.org/news/3600/the-x86-advanced-matrix-extension-…

Which hasn't kept them from building 64-bit cores with everything including AVX-512.. https://fuse.wikichip.org/news/3099/centaur-unveils-its-new-server-cla… IIRC you watch the "Rise of the Centaur" documentary they talk about the Intel lawsuit, and the corresponding counter suit that they won. Which makes the whole thing sound like MAD. More interesting there is https://en.wikichip.org/wiki/zhaoxin/kaixian

Not an expert, but it seems that the size of the logic wafer is locked to the size of the pixel wafer in Sony's CMOS image sensors? https://fuse.wikichip.org/news/763/iedm-2017-sonys-3-layer-stacked-cmo… ? It seems that 65nm was current-generation for CISes in 2018: https://www.azom.com/article.aspx?ArticleID=16321 .

The intel Kaby Lake G processors are Radeon RX Vega M GL/GH paired on-die with an 8th gen core series processor over an internal PCIE 3 x8 link. Seems like they could do much better, but its the only such product I know of. https://fuse.wikichip.org/news/1634/hot-chips-30-intel-kaby-lake-g/

AMD Zen 2 CPU and IBM z15 mainframe claims to be using TAGE branch predictor -- but this doesn't say much. The basic TAGE is quite simple (see [1]), but actual implementation likely includes loop predictor, statistical corrector predictor, perceptron hashing functions, etc. To learn more about state of start BP look for Andre Seznec (INRIA/IRISA) and Daniel Jimenez (Texas A&M University) work. They are usually the winners of Championship Branch Prediction [2,3]. [1] https://fuse.wikichip.org/news/2458/a-look-at-the-amd-zen-2-core/ [2] https://www.jilp.org/cbp2014/program.html [3] https://www.jilp.org/cbp2016/program.html

TSMC's original 7nm process 7FF did not use EUV. They did introduce EUV for certain layers in N7+, their "second generation" 7nm process. Don't confuse N7+ with N7P, the performance-improved version of 7FF.... There's more information at https://fuse.wikichip.org/news/2567/tsmc-talks-7nm-5nm-yield-and-next-… or https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/posts/… . (This is why I always try to give the full name of the process, in as much specificity as I know it; it's very easy to talk at cross purposes about N7+ and N7P despite them being quite different.)