Arm Community Blog

Great work! Popular narrative that NEON does not have a move mask alternative. Some time ago I published an article to simulate popular bit packing use cases with NEON with 1-2 instructions. This does not include unpacking cases but can be great for real world applications like compare+find, compare+iterate, compare+test. https://community.arm.com/arm-community-blogs/b/servers-and-cloud-comp…

> Vulkan 1.3 has pointers, thanks to buffer device address[1]. > [1] https://community.arm.com/arm-community-blogs/b/graphics-gam... "Using a pointer in a shader - In Vulkan GLSL, there is the GL_EXT_buffer_reference extension " That extension is utter garbage. I tried it. It was the last thing I tried before giving up on GLSL/Vulkan and switching to CUDA. It was the nail in the coffin that made me go "okay, if that's the best Vulkan can do, then I need to switch to CUDA". It's incredibly cumbersome, confusing and verbose. What's needed are regular, simple, C-like pointers.

They’re fast but that’s not usually why. ARM added some functions which could help with math-limited code: https://community.arm.com/arm-community-blogs/b/architectures-and-proc… Most JavaScript isn’t dependent on that specific a feature for performance, however. In most cases what matters more is that they have great memory performance and handle branch-heavy code well.

Really amazing work here! A colleague pointed out that FPAC[1] in ARMV8.6-A likely prevents this attack, is that right? I haven't fully digested the paper, but the gadgets seem to rely on AUT, and "Implementations with FPAC generate an exception on an AUT* instruction where the PAC is incorrect" [1] https://community.arm.com/arm-community-blogs/b/architectures-and-proc…

It's still true for compilers -- for instance gcc 10 had a greater than 10% perf improvement for AArch64 targets compared to gcc 9 as a result of various optimisation work: https://community.arm.com/developer/tools-software/tools/b/tools-softw…

> IMO it's more the flash than the CPU that puts the lower bound on power consumption with the smaller MCUs once you start sleeping. Agreed! There are some novel remarks on that in the link under "[1]" in my reply to the parent comment. Or see the following digest if paywalled: https://community.arm.com/developer/research/b/articles/posts/m0n0-an-…

It's a vast and complex topic. I once stumbled on the following presentation from ARM: https://community.arm.com/developer/research/b/articles/posts/the-ics-… The first part covers EUV, which is key to advanced nodes. Then it moves on to more futuristic and tentative techniques. But the EUV part is a nice introduction for non specialist, with pointers to dig if one is interested.

a) a57 is the "beefy" version of a53, it's significantly faster in raw performance so this should stomp an rpi - here's ARM's performance numbers at release: https://community.arm.com/cfs-file/__key/communityserver-blogs-compone… b) above the HDMI is displayport c) usb is 3.0 all around, great for NAS-style devices d) production module (for final product) uses 16gb emmc, whereas the devkit is microSD like rpi

Thanks for posting @hsiaoer and looking forward to your ML classification follow-up post. I've been focused on similar research and read with interest the ARM DynamIQ ML focus [0] as I believe this will open up ML edge processing on wearables, although hard to beat what Johny Srouji and team are doing. WatchOS 4 seems to support CoreML [1], do you plan to do inferencing on the device eventually? If so, cool! [0] https://community.arm.com/processors/b/blog/posts/arm-dynamiq-expandin… [1] https://developer.apple.com/library/content/releasenotes/General/Whats…

KASLR: Kernel Address Space Layout Randomization. See https://en.wikipedia.org/wiki/Address_space_layout_randomization for an overview on what this does. SMAP/SMEP: Intel/x86-specific security features. See http://j00ru.vexillium.org/?p=783 for an early (2011!) take on SMEP. (j00ru is great reading, in any case.) See https://lwn.net/Articles/517475/ for SMAP from LWN. PAN: Privileged Access Never, Basically ARM SMAP: https://community.arm.com/groups/processors/blog/2014/12/02/the-armv8-…

For ARM thumb2 style you need a third instruction between the two: IT EQ The 'IT' is for 'if then'. There could also be more 'then's and 'else's for the conditional execution of muliple instructions: ITTE LT (If then then else) The following instructions could for example be: ADDEQ ... STREQ ... BNE ... (Branch - not equal because of the else) Source: http://community.arm.com/groups/processors/blog/2010/09/30/condition-c…

This is for Cortex A8, which was the chip in the Nexus One. I wrote the original version of sound synthesis directly in ARM assembler[1]. It was very highly optimized, I remember using a cycle counting app that flagged any dependency chain that would cause the processor to stall, and ultimately utilization was in the 90%+ range. Back in those days, processors were simple enough you could do this kind of optimization by hand. By the time of Cortex A15 (Nexus 10 etc), instruction issue was out-of-order and much harder to reason about. The best current info I could find for the latency advice is [2]. Quoting, "Moving data from NEON to ARM registers is Cortex-A8 is expensive." Looking at [3] partially reveals the reason why: the NEON pipeline is entirely after the integer pipeline, so moves from integer to NEON are cheap, but the reverse direction is potentially a large pipeline stall. This is an unusual design decision that as far as I know is not true for any other CPUs. Edit: I found [4], which is a more authoritative source. [1]: https://github.com/google/music-synthesizer-for-android/blob/master/ap… [2]: https://community.arm.com/support-forums/f/armds-forum/757/neon-instru… [3]: https://www.design-reuse.com/articles/11580/architecture-and-implement… [4]:…

ARMv8.3-A added the new instruction LDAPR to allow acq_rel to be cheaper than seq_cst, so presumably it was worth adding. This summarises (https://community.arm.com/arm-community-blogs/b/architectures-and-proc… "The Armv8.0 support for release consistency is based around the “RCsc” (Release Consistency sequentially consistent) model described by Adve & Gharacholoo in [1], where the Acquire/Release instructions follow a sequentially consistent order with respect to each other. This is well aligned to the requirements of the C++11/C11 memory_order_seq_cst, which is the default ordering of atomics in C++11/C11." "Instructions are added as part of Armv8.3-A to support the weaker RCpc (Release Consistent processor consistent) model where it is permissible that a Store-Release followed by a Load-Acquire to a different address can be re-ordered. This model is supported by the use of memory_order_release/ memory_order_acquire /memory_order_acqrel in C++11/C11."

Every single thing released by Espressif is ground-breaking marvel. They are single-handedly moving the world, are a distinct Atlas upon the universe, lifting this Earth up. We are starting to see a couple low-cost would-be wifi System-on-Chip contendors. Realtek's RTL8720DN[1]. MediaTek was nominally going to be playing here[2] but has made almost no impact. Some few rare folks try to bring wifi to the world. But for the most part, there are dozens & dozens & dozens of fantastic, amazing, incredible, stupendous, delightful little microcontrollers in the world. But nearly none that embed wireless connectivity in a useful, usable fashion. It is so weird, that a strange, unloved bizarre architecture, Xtensa, happened to be the one architecture that some chip maker decided to add wifi to. But lordy & heavens, it has made all the difference. Espressif continues to build chips that do what no one elses chips do: connect. This is a pretty dramatic post, my apologies. I keep hoping wifi will become a more normal thing. I keep hoping chips traditionally sold for cell phones will start to get more love in the hobbyist market. Mid 2017, the "96boards" platform seemed to show hope for just that. An example was the HiKey 960, with a Huawei Kirin 960 octa-core chip with onboard wifi[3]. But the intervening three and a half years since then and now have been bleak. Access to good interesting modern chips has not increased. Folks like Espressif have remained not just a fallback, but the…

> Systems programming in any language would benefit immensely from better hardware accelerated bounds checking. [Mostly discussed deeper in the thread already but felt it was worth bringing up directly as a reply to this] This is an active area of development though still plenty of work to do. The Cambridge University Computer Lab have been doing research in this area in the form of CHERI: https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/ this gives you hardware capabilities which are effectively pointers with bounds given out by the OS. Want to access something? You need the appropriate capability to do so. ARM announced MTE last year, which whilst far less capable than CHERI begins to give you something (though it's targeted for bug hunting effectively rather than providing any actual security/safety properties): https://community.arm.com/developer/ip-products/processors/b/processor… ARM are also building a hardware CHERI implementation, Morello: https://developer.arm.com/architectures/cpu-architecture/a-profile/mor… There's already CHERI implementations running BSD on FPGAs, this will take it to the next level with real silicon using modern ARM processors (maybe you could run android on it for instance?). I think Intel have been looking along similar lines but I'm far less in touch with what they're up to so I don't have links.

Yes, ordered dither is easier in a shader than error diffusion, that's true, but error diffusion is definitely possible on a GPU. If you need it. Do you really need it? Why not still use the GPU to accelerate whatever parts you can? Even if you dither on the CPU, doing your color filters on the GPU instead of in JS could make the difference between interactive and not. I don't know what you're doing exactly, but when you do need dithering, it's usually the last thing you need to do before output, and it's usually less important that the dither is fast than most other operations you need in an image editor. BTW, random order is lower quality, and error diffusion is better, only for for very low res color palettes. If your result is more than 256 colors, it's irrelevant, and for high quality dithering, e.g., 16 bits per channel colors to 8 bits per channel for print, random ordered dithering is superior. https://community.arm.com/graphics/b/blog/posts/when-parallelism-gets-… http://www.cs.cmu.edu/~imisra/projects/dithering/HybridDithering.pdf https://www.shadertoy.com/view/4dt3W7 That last one is ugly, but it's a great proof of concept here. You could get error diffusion in a shader using 2 passes. The first pass you render to texture, and the second pass, you can sample the texture however you want. Note how in this example, the error diffusion propagates backwards from what you would normally do in JS or C++, because…

Allow me to refresh your memory then. How does the following sound to you? "We also support Full Profile and 64-bit natively, in hardware. After years of evangelising the benefits of such an approach it is nice to see other players in the industry join down this avenue." https://community.arm.com/groups/arm-mali-graphics/blog/2013/06/03/mal… "Mali-T622 was specifically tailored for this job. Mali-T622 also supports OpenCL Full Profile and includes double-precision FP64 and full IEEE-754-2008 floating-point support which are essential features in order to enhance the user experience" https://community.arm.com/groups/arm-mali-graphics/blog/2013/06/03/mal… I could go on with the examples but I think there's no need to spam the thread with tens of blog articles that say FP64 and "native 64-bit" (whatever that means) are essential to the mobile experience.

I know some of the Enlightenment core guys, and of course some of them work for Samsung; I've brought it up to them and it's safe to say that this is not a priority business case for them. They are all great folks, but with Samsung driving the train, I think this is no longer exclusively a volunteer project or necessarily strictly a labor of love for everyone anymore. That being said, it should work. I've successfully installed the dev kit from ARM-MALI support which provides Ubuntu + Mali T604 drivers on an SD card or USB (this was a herculean effort, despite the instructions in question being made specifically for the specific device I have). I haven't repeated this experiment, but I'd like to try again. I'd feel the chances it would work would be higher on Arch, where software is kept more up-to-date than on the ancient kernel and OS that ARM documentation suggested (it's Ubuntu, but not the current release, or even the current LTS release.) You probably already found this page[1] -- r6p0 seems to be newer than when I tried last, maybe you also saw this one[2] -- the best "from-scratch" resource I've found that results in a working graphics driver, but good luck getting a modern release of E20 to compile on that... perhaps it could be upgraded without breaking everything. This thread[3] I haven't visited for a while, but that chronicles my journey pretty well, at least prior to the point where I was trying ALARM or Arch Linux for ARM. The arch install guide[4] is…

This article 2 links deep had better technical details - https://community.arm.com/arm-community-blogs/b/mobile-graphics-and-ga… Upscaling solution mainly targeted at mobile gaming, with an 'AI pipeline' for upscaling graphics (They claim 540p upscaled to 1080p at 4ms per frame). I'm a bit skeptical because this is a press release for chips that are in the works and claim to be releasing in DEC-26, and then on actual devices after that. So sounds more like a strategic/political move (Perhaps stock price related manoeuvring). Unreal Engine 5 plugin will allow previewing the upscaled effects using the though, which will be nice for game developers.

Matter specifies that all firmware images must be signed so the device can verify authenticity before installation, ensuring they haven’t been tampered with. Matter further requires mechanisms to prevent unauthorized firmware execution and ensure that firmware can't be downgraded. Matter states that firmware images “may be encrypted.” This is not a requirement, though encryption is allowed and may add security (https://community.arm.com/arm-community-blogs/b/internet-of-things-blo…

ARM already have a special instruction `FJCVTZS` to accelerate JavaScript. If WebAssembly gets popular enough there will probably be hardware acceleration for it. https://community.arm.com/arm-community-blogs/b/architectures-and-proc… https://stackoverflow.com/questions/50966676/why-do-arm-chips-have-an-…

What you wrote doesn't make any sense. Arm has DTB [1]. Most SoCs re-use a lot of hardware IP blocks and they require very little modifications to DTB files in the kernel and device drivers to get them working. PCIe and USB support discoverability so no issue from that side. Arm ecosystem is cleaner in my experience and learned from the mistakes of the past. Arm CPUs are still not as fast as high-end x86 chips, but it's just a matter of time before that market is also eaten by Arm. [1] https://community.arm.com/oss-platforms/w/docs/525/device-tree

If you learn AVX2 programming via highload, my impression is that NEON is quite similar. The main difference is the lack of movemask. You can read these[0] articles[1] about what to do instead. For SVE, prior to very recent versions of SVE, there was no tblq (pshufb equivalent) so I didn't have much hope for using it for general-purpose programming, though of course it would be fine for stuff like TFA. [0]: https://community.arm.com/arm-community-blogs/b/infrastructure-solutio… [1]: https://www.corsix.org/content/whirlwind-tour-aarch64-vector-instructi…

I don't get why that guy didn't just link to a source, but I found this: https://en.wikipedia.org/wiki/Arm_Holdings#Founding The company was founded in November 1990 as Advanced RISC Machines Ltd and structured as a joint venture between Acorn Computers, Apple, and VLSI Technology. Which links a blog post and an LA Times news article as a source: https://community.arm.com/arm-community-blogs/b/architectures-and-proc… https://web.archive.org/web/20210325060916/https://www.latimes.com/arc…

I'm guessing that the "ML accelerator" in the CPU cores means one of ARM's SME extensions for matrix multiplication. SME in ARM v8.4-A adds dot product instructions. v8.6-A adds more, including BF16 support. https://community.arm.com/arm-community-blogs/b/architectures-and-proc…

I'm not an expert in this, but I don't think you'd be using similar hardware for video encoding and AI. Encoding uses a lot of compute, but it doesn't use much memory, whereas deep learning models (especially LLMs) use gobs of memory for both training and inference. If I had to guess, I'd speculate they're doing encoding on their Graviton ARM CPUs: https://community.arm.com/arm-community-blogs/b/infrastructure-solutio…

Arm Cortex-R series is intended to very hard real-time, and do branch prediction only if explicitly enabled > However, the Cortex-R7 and Cortex-R8 do not enable branch prediction automatically at reset. This means software must enable branch prediction to get the maximum hardware performance. https://community.arm.com/arm-community-blogs/b/architectures-and-proc… Its still OoO but idk how much that impacts anything Edit: apparently only r7/8 were ooo, r52/82 are in-order again

I am the author of this trick as well You can read about it in https://community.arm.com/arm-community-blogs/b/infrastructure-solutio…

Some folks may be interested in the Armv9 Scalable Matrix Extensions which appear to do something very very similar. https://community.arm.com/arm-community-blogs/b/architectures-and-proc…

Wrong answer. AMX is an unstable ISA that changes between product generations. That's why it's not publicly documented. Arm SME is the standardisation of the concept, but is not inmarket yet. https://community.arm.com/arm-community-blogs/b/architectures-and-proc…