Alexander Yee

I agree. I work in a similar field, and the value of AVX512 is clearly there - it just hasn't been worth implementing for the tiny percentage of market penetration. This is directly due to the market segmentation strategy Intel applied. AMD has raised the ante for AVX512 with two excellent implementations in a row, and for the first time ever I'm definitely considering building AVX512 targets. Just as a small example from current code, the much more powerful AVX512 byte-granular two register source shuffles (vpermt2b) are very tempting for hashing/lookup table code, turning a current perf bottleneck into something that doesn't even show up in the profiler. And according to (http://www.numberworld.org/blogs/2024_8_7_zen5_avx512_teardown/) Zen5 has not one but _TWO_ of them, at a throughput quadrupling Intel's best effort..

I found it, but clicking it caused my computer to run out of available memory. Edit: on a more serious note, a site[0] that tracks these records says: > Downloading of digits is no longer available due to the massive bandwidth requirements. Your best bet is to directly contact one of the record holders and see if they still have a copy of the digits. [0] http://www.numberworld.org/digits/Pi

If you have the opportunity, try out a zen5. Significant improvements. See also https://www.numberworld.org/blogs/2024_8_7_zen5_avx512_teardown/

That's assuming 1 IPC, and no parallelism. A desktop-class zen5 CPU has 32 threads, with AVX512. Pipelining gets you up to 2048 bits of SIMD throughput per core per clock cycle: https://www.numberworld.org/blogs/2024_8_7_zen5_avx512_teardown/ So assuming you use 64-bit counters, you can divide those 12 years by 1024 to get 4 days. And that's not even considering what you could do on a GPU. Edit: I might be off by a factor of 2, not sure if the SIMD throughput is per-core or per-thread. Also thermal throttling. Same ballpark though!

The announcement from y-cruncher (The first scalable multi-threaded Pi-benchmark for multi-core systems) https://www.numberworld.org/y-cruncher/news/2025.html#2025_5_16

The instruction is VP2INTERSECT. Note this instruction may not be supported by Intel processors after Tiger Lake. https://www.felixcloutier.com/x86/vp2intersectd:vp2intersectq http://www.numberworld.org/blogs/2024_8_7_zen5_avx512_teardown/#VP2INT…

> But AMD's implementation doesn't seem to have this problem From an article: > Does Zen5 throttle under AVX512? > Yes it does. Intel couldn't get away from this, and neither can AMD. Laws of physics are the laws of physics. > The difference is how AMD does the throttling ... Further details in the article [1]. Discussed here on HN: [2], [3]. [1] https://www.numberworld.org/blogs/2024_8_7_zen5_avx512_teardown/ [2] https://news.ycombinator.com/item?id=41182395 [3] https://news.ycombinator.com/item?id=41248260

It's in his bio. "However, ever since grade school, I've always sucked in terms of grades and standardized tests. I graduated from Palo Alto High School in the bottom quartile among all the college-bound students. My GPA was barely a 3.0 at graduation, so it was somewhat miraculous that I got accepted into Northwestern University at all."[1] I know he has a masters and all, but he is spectacular. Hundreds of thousands of people have masters degrees. He is more impressive than 99% of professors, and academia doesn't even acknowledge him as a peer of them. [1] http://www.numberworld.org/about/ayee/

How does it compare to converting each number to a large fixed-point integer (implemented as N 64-bit integers), summing them with exact integer math (order-invariant), and converting back to floating point at the end? The sum part can be done with AVX-512 [1] if N=8, and N=8 is probably enough for a lot of real world summations. The conversion back to floating point at the end is only done once so not very costly. The conversion to fixed point is probably the worst part. Is there a faster way to do it than a loop that extracts one 64-bit integer per iteration? If not we could convert several input numbers at a time with SIMD. But it would be nifty to be able to convert one double to N integers with SIMD instead of a loop. [1] http://www.numberworld.org/y-cruncher/internals/addition.html#ks_add

Just wanted to mention that SuperPi - the benchmark that is very widely used for at least a decade for measuring PC / CPU single threaded performance uses the same algorithm so not really obscure. That said, multi threaded algorithms make more sense for modern multi core computer architectures, something like this for example: http://www.numberworld.org/y-cruncher/

When I googled digits of pi I found http://www.numberworld.org/y-cruncher/ where they get 25M digits in about one second (rather than one minute) depending on what kind of computer you use.

It should be noted that y-cruncher, that closed-source program, is responsible for every pi computation record since 2010 (back then the record was 2.7T digits). Traditionally these records were held by supercomputers, but it seems that pi computation is no longer a good way to benchmark or stress-test them [1], leaving only interested individuals in the scene. If pi computation were useful by its own, or there were a lot of people working towards records, we can expect multiple competitive pi computation programs where some of them are hopefully F/OSS. (The algorithm itself is not exactly secret anyway and big ideas are already in public, what makes y-cruncher special is its meticulous optimization.) But I don't see anything like that. There seem no actual demands for pi computation software, not just F/OSS. [1] http://numberworld.org/y-cruncher/faq.html#why_desktops

It appears they have, the y-cruncher program he used does verification. Alexander Yee, who wrote the y-cruncher program (which has been used for the previous 4 world record calculations of digits of Pi), has accepted it and posted it on their site, along with screenshots of the output of the program. http://www.numberworld.org/y-cruncher/

http://www.numberworld.org/y-cruncher/ (Mostly closed source)

Alexander Yee's writeup is interesting – CPU utilisation was only about 12%, they encountered quite nasty I/O bottlenecks (particularly for writes.) http://www.numberworld.org/blogs/2019_3_14_pi_record/ Contradicts the Google blog a little, especially where he points out that they hit performance issues with live migration (Google said it worked fine without impact on the application.)

I wondered the same, according to the site its not possible to parallelize: http://www.numberworld.org/y-cruncher/faq.html#distributed The nth digit type computations are too slow.

For the 12.1*10^12 calculation the refernced web site says: Hudnovsky algorithm [1] for the calculation, Bellard BBP formula for verification. Implementation in the programm y-cruncher "A Multi-Threaded Pi-Programy-chruncher" [3] For the math see [4] also. [1] https://en.wikipedia.org/wiki/Chudnovsky_algorithm [2] https://en.wikipedia.org/wiki/Bellard%27s_formula [3] http://www.numberworld.org/y-cruncher/ [4] http://www.numberworld.org/misc_runs/pi-5t/details.html#formulas

Check out the "Object Types" section of http://www.numberworld.org/ymp/v1.0/documentation/objects.html The program has it's own types for arbitrary precision ints and floats.

> If you have some piece of code in a different security context that conditionally executes a heavy instruction based on a decision made over some sensitive data, doesn't this provide a way to obtain information about that data? Yes. http://www.numberworld.org/blogs/2018_6_16_avx_spectre/

The software they used is linked and has a some info about the internals here: http://www.numberworld.org/y-cruncher/algorithms.html

There used to be five hundred billion digits of e available here[1], which would remove this reason to think something strange was happening, not that it would prove it. [1] http://www.numberworld.org/digits/E/

Interesting idea. Actually, just thinking, could be used for a pseudo-crypto app. Just send a series of origin numbers [n1,n2,n3...] and this translates to [pos1,pos2,pos3...] series of numbers. You can use also instead of Pi any other transcendental/irrational number [0]. [0] http://www.numberworld.org/digits/

You meant to link to http://www.numberworld.org/misc_runs/pi-10t/details.html

More information about the setup: http://www.numberworld.org/misc_runs/pi-5t/details.html

This http://www.numberworld.org/misc_runs/pi-5t/details.html has got the specs of the computer he used to calculate 5 trillion places.

Here's my quick take. A top of the line Zen core is a powerful CPU with wide SIMD (AVX-512 is 16 lanes of 32 bit quantities), significant superscalar parallelism (capable of issuing approximately 4 SIMD operations per clock), and a high clock rate (over 5GHz). There isn't a lot of confusion about what constitutes a "core," though multithreading can inflate the "thread" count. See [1] for a detailed analysis of the Zen 5 line. A single Granite Ridge core has peak 32 bit multiply-add performance of about 730 GFLOPS. Nvidia, by contrast, uses the marketing term "core" to refer to a single SIMD lane. Their GPUs are organized as 32 SIMD lanes grouped into each "warp," and 4 warps grouped into a Streaming Multiprocessor (SM). CPU and GPU architectures can't be directly compared, but just going by peak floating point performance, the most comparable granularity to a CPU core is the SM. A warp is in some ways more powerful than a CPU core (generally wider SIMD, larger register file, more local SRAM, better latency hiding) but in other ways less (much less superscalar parallelism, lower clock, around 2.5GHz). A 4090 has 128 SMs, which is a lot and goes a long way to explaining why a GPU has so much throughput. A 1080, by contrast, has 20 SMs - still a goodly number but not mind-meltingly bigger than a high end CPU. See the Nvidia Ada whitepaper [2] for an extremely detailed breakdown of 4090 specs (among other things). A single Nvidia 4090 "core" has peak 32 bit multiply-add…

Expanding on 3: I think it ends up at O(n^2 * log n) transistors, O(log n) critical path (not sure on routing or what fan-out issues might there be). Basically: determine end of instruction at each byte (trivial but expensive). Determine end of two instructions at each byte via end2[i]=end[end[i]]. Then end4[i]=end2[end2[i]], etc, log times. That's essentially log(n) shuffles. With 32-byte/cycle decode that's roughy five 'vpermb ymm's, which is rather expensive (though various forms of shortcuts should exist - for the larger layers direct chasing is probably feasible, and for the smaller ones some special-casing of single-byte instructions could work). And, actually, given the mention of O(log n)-transistor shuffles at http://www.numberworld.org/blogs/2024_8_7_zen5_avx512_teardown/, it might even just be O(n * log^2(n)) transistors. Importantly, x86 itself plays no part in the non-trivial part. It applies equqlly to the RISC-V compressed extension, just with a smaller constant.

Intel's argument is exactly that you cannot recognize whether a CPU is not degraded at all or it is partially degraded. Anecdata point: my 13900K system is a couple of years old, with a December 2022 in-service date, and has been rock solid in everyday use. Until I ran the http://www.numberworld.org/y-cruncher/ benchmark, which reported errors after about an hour. So for users of the affected CPUs, it may be smart to repeat that experiment before assuming they have "one of the good ones." At this point I'm left wondering how long it will be before faults appear during normal workloads. The CPUs that have not been overclocked are unlikely to have been degraded. That is absolutely not the case. My system is running bog-standard BIOS settings from an OEM known to be conservative in that regard (Puget Systems). Among the many reports of problems, there have been quite a few from cloud providers, who don't overclock their systems as a rule.

We already have 128-bit processors, of sorts. They are called "vector units". ;) 128-bit integers could be useful for bignums. You can do bignum addition on existing SIMD units but you'd have to use tricks to carry the carry between elements and to the next vector — and that makes the resulting code slower than using GPRs.[1] But I think this would still fit better in vector units than making the integer registers larger: The hw trend (ARM SVE, RISC-V V) is to make vector-width implementation-defined, starting at 128 bits in the low-end. 128-bit floating point is apparently a thing in scientific computing (but I've not seen it myself). 128-bit "pointers" exist in CHERI [2], where they are tagged capabilities that also store the bounds and access rights (rwx) for accessing memory through the pointer. Addresses are still 64-bit though. GPRs are still 64-bit. The caps are stored in a new register file. If you want to scale up address spaces, I think the biggest issue is not the number of bits but rather how to coordinate the address space to avoid collisions. One approach would be to re-introduce segmentation (pointer ⇒ segment ID and offset within segment), but unlike earlier system make each segment have its own local namespace of segment IDs it knows and translate between those when transferring pointers between segments. This idea is used by e.g. the research OS "Twizzer" [3], which was made for a large address space using NVRAM as RAM. I think this "pointer swizzling"…