Mill Computing Blog

For those that don't know about the Mill see https://millcomputing.com/ I came to this thread looking for a comment about this. I've been patiently following along for over a decade now and I'm not optimistic anything will come from the project :(

You must be astroturfing (or whatever it's called - submarining, secretly shilling, etc.) for the Mill project[0]! ;) Every once in a blue moon someone from that group returns from "investing sweat equity into patents" (or however they're [not] getting paid for whatever they're doing) to HN's reality distortion field (welcome!) and blesses us with wisdom[1] from their awe-inspiring project currently classified as vaporware by many such as myself with no public evidence of even a single physical hardware prototype. I would be interested to hear your thoughts about that project, and also hope my playful jab (not too harsh?) can provoke any of them to respond to your comments (maybe they should hire you!). There are other projects mentioned in those comments that you may find interesting as well (CheriBSD, L4 Linux, etc.) Also, any thoughts you have time to share on the adaptability of the various open hardware RISCV projects, which seem to be at the beginning stages of delivering just beyond basic functionality without much priority allocated for your secure performance concerns. I was surprised to see no specific mention of it in your initial​ comment. To the best of my very limited knowledge, a genuinely secure processor, even versus nation-state level actors, is unfortunately still non-existent or near uselessly underperformant (is that a word?) at this point. Not to mention all of the various other, often easily side-channel attacked, bits and pieces are required to…

Reminds me of Mill Computing's stuff. https://millcomputing.com/

The title really confused me until I realized this has nothing to do with https://millcomputing.com/ :-)

I wonder if the 7th edition will cover the Mill CPU. It should but I doubt it will. https://millcomputing.com

CDC 6000 was a barrel processor: https://en.m.wikipedia.org/wiki/Barrel_processor Mill CPU (so far only patent-ware but interesting nevertheless) : https://millcomputing.com/

The mill architecture has interesting ideas but as far as I know it’s never made it past simulation and there hasn’t been much progress lately. https://millcomputing.com/

I should also have mentioned The Mill architecture as an example of dealing with code as blocks of instructions instead of each one separately. In this case they get a higher fetch rate for their VLIW machine by starting execution from the middle of the block and fetching both up and down at the same time. So they have two program counters which get set to the same value on every jump or call. https://millcomputing.com/ The point is that inside every advanced processor instructions are handled in groups and if you expose that to the compiler you can save transistors and energy.

What excites me most about RISC-V is the ability to potentially experiment at a systems level. I love the Mill project and they have a ton of interesting and clever ideas but they're trying to innovate along so many dimensions at once that I feel like it's almost a forgone conclusion that they'll fail. What I'd really like is for someone to design a chip with their ideas about backless memory and putting address translation at cache/memory border and do a RISC-V implementation of that. Then you could try getting a working OS with that up, and then maybe incrementally try out other ideas rather than just trying to change the world all at once. We've had this paradigm about how memory and permission and OS resource management works that we've have since the PDP-11 and I think we ought to be looking at how to move beyond that. http://millcomputing.com/wiki/Memory

Talks on the Mill CPU architecture: https://www.youtube.com/playlist?list=PLFls3Q5bBInj_FfNLrV7gGdVtikeGoU… See also: https://millcomputing.com/docs/ Ivan Godard is a pretty good speaker, and his discussion of how the Mill CPU works is very insightful if you are at all interested in modern CPUs work. I don't know that we'll ever see Mill CPUs in wide use (I've been focusing on RISC-V), but there are so many interesting ideas presented in this video series. Ideas that will leave you asking: "Why do we do things the way we do now?" over and over again. One of the most interesting ideas is how the Mill CPU architecture takes into account the 2D nature of silicon lithography.

Likely vaporware at this point, but no discussion of chip startups is complete without mentioning Mill Computing: https://millcomputing.com/ It would represent a true architectural revolution if it ever actually came to fruition. Lots of past discussion on HackerNews over the decade(!) it’s been under development.

This reminds me that it's been a while since I've checked in on the belt machine that Ivan Godard & friends were working on at Mill Computing. It looks like their website has change a bit since I last looked: https://millcomputing.com/

You should look into the Mill CPU architecture.[0] Its design should make microkernels much more viable. * Single 64-bit address space. Caches use virtual addresses. * Because of that, the TLB is moved after the last level cache, so it's not on the critical path. * There's instead a PLB (protection lookaside buffer), which can be searched in parallel with cache lookup. (Technically, there's three: two instruction PLBs and one data PLB.) [0]: https://millcomputing.com/

I kept reading but I did have a "hey, that's kind of unfair" reaction at that line. It's not their fault that the speed of light is a hard limit, eh? There's a chicken and egg problem with compilers and languages on the one side and machines architectures and instruction sets on the other, it's not easy breaking the mold. (GPUs are a counter-example perhaps?) CPU designers can't all be Ivan Godard ( https://hackaday.com/2013/08/02/the-mill-cpu-architecture/ https://millcomputing.com/ ) or Chuck Moore ( https://en.wikipedia.org/wiki/Charles_H._Moore#Hardware_design http://www.greenarraychips.com/ ) eh?

I haven't worked for them for a few years now but it's still a "sweat equity" organization as described on the web page under "About" at https://millcomputing.com/ They consider investments for their minimal costs as well.

Maybe the Mill? https://millcomputing.com/ edit: added link.

> As the architects of the Motorola 68000 and iAPX-432 both learned, the marketplace is rarely patient. I hope this won't mean the Mill has no chance of success, or at least influencing the industry for the better. Every video seems to introduce interesting new ideas, or new takes on old ideas[0]. https://millcomputing.com/

A next chapter is in need of being written, as the Mill is a radical departure (non-OOO), and a wildly more efficient and secure architecture, first published since 2014 (see https://millcomputing.com/ videos).

Would the mill architecture avoid this bottleneck? https://millcomputing.com

Not to be confused with the Mill Computer Architecture: https://en.wikipedia.org/wiki/Mill_architecture, https://millcomputing.com/.

Why do you think such an architecture is completely invulnerable? The Summary #2 slide lists the following as a benefit of the Mill: - Can load across protection boundaries Valid data is usable; invalid data cannot be seen At the very least, this probably makes ASLR pretty easy to defeat across protection boundaries. Are you really willing to bet that there will never be a more clever exploit that can determine more information? In slide 51 of the IPC talk[0] they explicitly say that they put permissions checking after the cache, and that this is essential for their performance and power claims. [0] https://millcomputing.com/docs/inter-process-communication/

This forum post is the best summary I've seen: https://millcomputing.com/topic/introduction-to-the-mill-cpu-programmi… It links to videos with longer explanations.

It's an interesting question, maybe ask at the Mill forum: https://millcomputing.com/forum/the-mill/ Based on my limited understanding of the Mill I'd say (1) (simple_ PHIs are implemented by the pick-phase, (2) it's an exposed pipeline with known latencies, so you can't really have the "I want to avoid the longer latency inside a single basic block", and it's probably not worth doing that for a single mult vs. a single add, (3) for cases where it matters because the latency difference is much better, you'd use two basic blocks, and rearrange belt positions at the end.

http://millcomputing.com/#JoinUs :) http://millcomputing.com/topic/mill-computing-in-2017/ is our plan this year

A promising alternate architecture that places some previously features in hardware [1]. The execution model still closely matches current architectures. See also different approaches to programming that make space-time tradeoffs more explicit [2], and use natural-law like principles to distribute computing across a simpler but highly connected computing fabric. [1] https://millcomputing.com/ [2] http://web.mit.edu/jakebeal/www/Publications/PTRSA2015-Space-Time-Prog… [3] http://blob.lri.fr/

There really hasn't been anything to follow apart from the video lectures (https://millcomputing.com/technology/docs/).

What you are looking for is called the Mill: https://millcomputing.com/

A sea of ALUs with an instruction set to directly route them together, is effectively describing the Mill CPU. http://millcomputing.com/

The Mill CPU (http://millcomputing.com/) seems to be going down both those routes- it's a very in-order, VLIW-like design with some tweaks to make it work well with typical OOE workloads, including several ways to make the encoding much smaller.

I want a Coq kernel! But seriously, I'm not sure writing the stuff in assembly can also optimise simplicity and manageability. Though we are talking about the obsolete X86 architecture here. More reasonable hardware[1] will likely be easier to compile to. [1]: http://millcomputing.com/