Tavian Barnes
tavianator.com · Personal blog · on HN since 2011
Tavian Barnes, a software engineer, writes about low-level performance, CPU quirks, Rust, and algorithms.
What HN saysHN commenters link his explanation of the Alder Lake SHLX anomaly and his ray-box intersection post, which relies on IEEE 754 infinity behavior.
27HN people shared it
4linked it in comments
30stories submitted
814story points
1 year agolast shared
2011people per year2026
Most-shared posts
- 1Irregular Expressions3 people · 12 points · first shared 2023 · 3 comments on HN
- 2Proving that 1 plus 1 equals 10 in Rust3 people · 4 points · first shared 2020 · discussion on HN
- 3The Alder Lake SHLX Anomaly2 people · 234 points · first shared 2025 · 74 comments on HN
- 4The Alder Lake anomaly, explained2 people · 8 points · first shared 2025 · 9 comments on HN
- 5Cracking DHCE (Diffie-Hellman color exchange)2 people · 7 points · first shared 2018 · discussion on HN
- 6You could have invented futexes2 people · 2 points · first shared 2023 · discussion on HN
- 7Ray box2 people · first shared 2021
- 8Bug hunting in Btrfs1 people · 243 points · first shared 2024 · 204 comments on HN
- 9Parallel ./configure1 people · 219 points · first shared 2025 · 186 comments on HN
- 10Rounding Percentages1 people · 47 points · first shared 2024 · 27 comments on HN
- 11Sneaky Git Commits1 people · 8 points · first shared 2025 · 2 comments on HN
- 12BFS – “find” replacement which does breadth-first search (2016)1 people · 5 points · first shared 2019 · 1 comments on HN
- 13Spawn() of Satan1 people · 3 points · first shared 2018 · discussion on HN
- 14Long Division1 people · 3 points · first shared 2022 · discussion on HN
- 15Porting k-d forests to Rust1 people · 3 points · first shared 2020 · discussion on HN
What HN people wrote when they linked it
remexre · 2025-09-08
> Maybe RISC-V?
RISC-V is specified as a RISC (and allows very space-/power-efficient lower-end designs with the classic RISC design), but designed with macro-op fusion in mind, which gets you closer to a CISC decoder and EUs.
It's a nice place to be in tooling-wise, but it seems too early to say definitively what extensions will need to be added to get 12900K/9950X/M4 -tier performance-per-core.
In either case though, a bunch of the tricks that make modern CPUs fast are ISA-independent; stuff like branch prediction or [0] don't depend on the ISA, and can "work around" needing more instructions to do certain tasks, for one side or the other.
[0]: https://tavianator.com/2025/shlx.html
tavianator · 2025-01-04
Wrote up the presumed explanation here: https://tavianator.com/2025/shlxplained.html
magicalhippo · 2023-09-27
In IEEE 754, division by zero is well defined[1], and some algorithms rely on this[2].
Not sure how it relates to frame lag, some less-than-ideally-implemented iterative routine?
[1]: https://en.wikipedia.org/wiki/IEEE_754#Infinities
[2]: https://tavianator.com/2011/ray_box.html
ChrisLomont · 2021-10-20
There are algorithms that behave correctly but require intermediate Inf or NaN to work. If I recall there is one related to finding bounding box intersections in ray tracing. I know when I introduce such code into a codebase I put a large "DO NOT CHANGE THIS..." style comment with an explanation so some enterprising programmer doesn't put some if statements in to remove what they think is an error, when it is not.
I'd suspect the same is true for NaN. These things were introduced for reasons. If you don't have a deep knowledge of why, don't assume everyone else is the same.
Edit: I found examples using a NaN and Inf intermediates to get a large speed increase [1,2].
[1] https://tavianator.com/2015/ray_box_nan.html
[2] https://tavianator.com/2011/ray_box.html