Talospace

Now this is a nice surprise!! Really happy to know I'm not alone out there! Looks like Dr. Kaiser is also a primary care physician, also a C programmer and also all about owning the computer. In addition to everything you've listed, he's also done serious work on POWER9 which is amazing!! https://www.talospace.com/2018/11/roadgeeking-with-talos-ii-or.html

My understanding is there's issues around POWER10 that stopped it from being adopted: https://www.talospace.com/2021/09/its-not-just-omi-thats-trouble-with.… . For me personally, having worked enough with embedded POWER chips to get weirdly comfortable with ISA, given the choice, I'd love to have a system like this to write pure ASM stuff on. Not for any practical reason in the slightest; pretty much in the same spirit of souping up a go kart. On that note, out of curiosity, how do these compare with x86 and ARM chips from that era?

It's a full-blown workstation. If you're interested, https://www.talospace.com/ is a blog covering developments in the POWER sphere, including reviews of applications, games and OSs running thereon.

Don't forget that POWER10 is no longer ryf-certifiable. Of course the ryf certification may be questionable but it is an established bar, POWER9 was able to cross it, POWER10 probably won't: https://www.talospace.com/2020/08/power10-sounds-really-great-but.html https://twitter.com/RaptorCompSys/status/1435510763402244105?ref_src=t…

He's got multiple power9 systems, he regularly blogs about it at https://www.talospace.com/

Powerful 22-core, 18-core server-grade systems with fully open firmware and hardware, fully open BMC, with PCIe 4.0, DDR4 memory with ECC and other modern features [1]. They are FSF RYF (Respects Your Freedom) certified [2]. Truly FOSS hardware. Quite affordable too. I think not many have heard of it. They have fully FOSS desktop processors too (4-core, 8-core). [1] https://www.raptorcs.com/ [2] https://ryf.fsf.org/vendors/raptor More info: [3] https://wiki.raptorcs.com/wiki/Main_Page [4] https://www.talospace.com/ [5] #talos-workstation on IRC, where people using these systems daily hangout. Accessible through the Element Matrix app IRC bridge too. Now idk whether that's innovation, but it's a big thing IMO. AMD, Intel and ARM have proprietary bits in them that can potentially spy on your entire system (AMD Platform Security Processor, Intel Management Engine)

Regarding Raptor... https://www.talospace.com/2020/08/power10-sounds-really-great-but.html… https://www.talospace.com/2020/07/condor-cancelled.html?m=1#comments Were there ever any updates to that rather pessimistic blog post?

new web browser for PowerPC Mac: http://www.floodgap.com/software/tenfourfox/ new OS for PowerPC Mac: https://voidlinux-ppc.org/ or, a new PowerPC computer: https://www.talospace.com/

I would have killed for the handcrank during the G1G1 days, but it turns out it wasn't _completely_ vapourware. I finally saw a working one at Linux SCaLE 17x years after the fact, so I'm assuming some small number must actually have been produced. It wasn't practical, but I still love the concept. https://www.talospace.com/2019/03/a-close-look-at-raptor-blackbird-and…

Whilst it is true indeed that POWER10 requires an opaque blob of firmware goo, Raptor was supposed to bring a follow-up to POWER9 that uses the Solid Silicon S1[0] instead of POWER10: Raptor yesterday officially announced that we're not getting Power10 systems. The idea is we're going to be getting something better: the Solid Silicon S1. It's Power ISA 3.1 and fully compatible, but it's also a fully blob-free OpenPOWER successor to the POWER9, avoiding Power10's notorious binary firmware requirement for OMI RAM and I/O. […] the S1's specs, and he said it's a PCIe 5.0 DDR5 part running from the high 3GHz to low 4GHz clock range, with the exact frequency range to be determined. (OMI-based RAM not required!) The S1 is bi-endian, SMT-4 and will support at least two sockets with an 18-core option confirmed for certain and others to be evaluated. This compares very well with the Power10, which is also PCIe 5.0, also available as SMT-4 (though it has an SMT-8 option), and also clocks somewhere between 3.5GHz and 4GHz. I have not heard of Solid Silicon before, and their website[1] does not reveal much other than indirectly ascertaining the non-laptop factor of the S1 SoC(?). [0] https://www.talospace.com/2023/10/the-next-raptor-openpower-systems-ar… [1] https://www.solidsilicon.com/desktop/index.html

Didn’t POWER end up needing proprietary memory firmware? https://www.talospace.com/2021/09/its-not-just-omi-thats-trouble-with.… That couldn’t have helped. Otherwise I feel like RISC-V is better if you want to build something new from scratch.

They ended up going with a different platform that's still newer than Power9. It's even bi-endian. https://www.talospace.com/2023/10/the-next-raptor-openpower-systems-ar…

> I guess that is also the issue with Power10 here that causes Raptor to go its own way. I thought avoiding the POWER10 was the result of firmware blobs. [0][1] "While we applaud the overall extent of source code available for the #POWER10 firmware stack, two key P10-specific firmware components remain closed source at this time. The first is the off-chip OMI DRAM bridge, and the second is the on-chip PPE I/O processor" [2] [0] https://www.devever.net/~hl/omi [1] https://www.talospace.com/2021/09/its-not-just-omi-thats-trouble-with.… [2] https://twitter.com/RaptorCompSys/status/1435510763402244105

Let me be more specific. There were a lot of bugs specifically related to non-4k page size architectures. Arm doesn't dictate the page size so most of the Arm systems out there have defaulted to 4k pages. The Asahi wiki has a partial list of userspace programs that were (or still are) buggy and broken because they made simplifying assumptions about how different architectures work[0]. Maintainers of other non-x86 architecture have said that this is improving things for them[1]. [0]: https://github.com/AsahiLinux/docs/wiki/Broken-Software [1]: https://www.talospace.com/2022/03/asahi-linux-gives-hope-for-weird-pag…

It's size is what turned me off most about the devterm. I would be much more tempted by a device just a bit bigger. This[1] blog post has good pictures, one next to a DVD case for size comparison. [1] https://www.talospace.com/2022/05/mini-review-clockwork-pi-devterm-r-0…

There are some issues with Power10, although Raptor hasn’t revealed them yet until they clarify things with IBM: https://www.talospace.com/2020/07/condor-cancelled.html?showComment=15…

Void Linux as well: https://www.talospace.com/2019/01/void-linux-goes-power9.html Although it's not official at this point I don't think.

For those who are not familiar with the author of this blog, he is a PowerPC enthusiast and the maintainer of TenFourFox, a Firefox port to PPC OS X. He's also currently working on a new PPC JIT for (modern) Firefox on Linux (a project for which he is looking for volunteers to assist him[1]) to bring it to speed parity with Chrome on PPC (which already has a PPC JIT). [1] https://www.talospace.com/2019/03/pitch-into-firefox-jit.html

Thank you for documenting exactly how some of the more absurd bugs we encounter in the wild might actually happen. :) E.g. https://www.talospace.com/2019/04/broadcom-bcm5719-libre-firmware-comi…

I have only skimmed these articles, but they address your question regarding POWER: https://wiki.raptorcs.com/wiki/Speculative_Execution_Vulnerabilities_o… https://www.ibm.com/blogs/psirt/potential-impact-processors-power-fami… https://www.talospace.com/2018/08/l1-terminal-fault-another-good-day-t… http://tenfourfox.blogspot.com/2018/07/netspectre-not-much-of-powerpc-… http://tenfourfox.blogspot.com/2018/01/actual-field-testing-of-spectre… http://tenfourfox.blogspot.com/2018/01/more-about-spectre-and-powerpc-… http://tenfourfox.blogspot.com/2018/01/is-powerpc-susceptible-to-spect… The _Talospace_ and _TenFourFox Development_ articles are by Cameron Kaiser, who is active on HN (and Blogger) as classichasclass. Edit: Add missing 'and' in last sentence.

Hopefully the new ISA will continue to support tagged memory pointers (capability computing), which can stop many security attacks, https://www.talospace.com/2022/10/power9-and-tagged-memory-and-why-you… & https://www.devever.net/~hl/ppcas > IBM's capability-based design is implemented using a hybrid of both hardware and software. The central premise of the design is that you cannot write native code for the platform directly; instead, all programs for the system must be written in an intermediate language which is translated internally (at installation time) to Power ISA machine code by the system's “kernel”. This trusted translator maintains the desired security invariants of the system, just like the modern sandboxed JIT designs used in Java, .NET, JavaScript and WebAssembly, and without relying on hardware memory protection. > In order to support this capability-based OS, IBM implemented an undocumented extension to the Power ISA known as PowerPC AS. This ISA extension provides a memory tagging system which associates one tag bit with every aligned 16 bytes of system memory (a quadword). In a 128-bit pointer, 64 bits are used for the typical memory address; the other half stores a few bits of metadata and is otherwise reserved (the degree of futureproofing is rather extreme). HN discussion (2022), https://news.ycombinator.com/item?id=33381823

From 2012: https://www.wired.com/2012/08/nasa-patch/ This has likely changed, especially after this most recent update, but: > "The process took four days" > "On the first day of the software update, the team deployed a temporary version of the new software to the rover's primary computer. This version was only held in RAM so that the computer would revert back to the previous version when it restarted. This gave the team a chance to make sure everything was functioning properly. On the second day the team deployed a more permanent version of the update to the computer's file system. On the third day they deployed the temporary version to the backup computer and on the fourth day they deployed the permanent version to the backup computer." > "every interaction takes about 30 minutes: 14 minutes to send a signal to the rover in space, 14 minutes to get a response" > "it only took a few minutes for the software to actually install" --- On the hardware: https://venturebeat.com/business/sending-a-software-update-through-spa… > "Curiosity Rover is powered by a pair of computers built by BAE Systems. These RAD750 computers use a 10-year-old IBM PowerPC microprocessor running at 132 megahertz. It has just 120 megabytes of random access memory... doesn’t have enough memory for both the landing and surface missions" NASA have been using RAD750s since 2005, most recently on JWST. BAE has a successor in the RAD510, but it looks like NASA are…