gms.tf
gms.tf · Personal blog · on HN since 2018
The personal technical blog at gms.tf covers RISC-V, Linux internals, build tools like Meson, and small hardware and audio projects.
What HN saysHN commenters cite its RISC-V vector article to explain vector-length-agnostic design, and discuss its syscall cost measurements across different CPUs.
16HN people shared it
7linked it in comments
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What HN people wrote when they linked it
menaerus · 2025-09-27
Where is the state/registers written to then if not L1? I'm confused.
What do you say about the measurements from https://gms.tf/on-the-costs-of-syscalls.html? Table suggests that the cost is by a magnitude larger, depending on the CPU host, from 250 to 620ns.
photochemsyn · 2023-06-01
This looks like a curious case, non-fixed-length vectorization code in RISC-V:
> "Perhaps the most interesting part of the open RISC-V instruction set architecture (ISA) is the vector extension (RISC-V "V"). In contrast to the average single-instruction multipe-data (SIMD) instruction set, RISC-V vector instructions are vector length agnostic (VLA). Thus, a RISC-V "V" CPU is flexible in choosing a vector register size while RISC-V "V" binary code is portable between different CPU implementations."
https://gms.tf/riscv-vector.html
ZeroCool2u · 2023-03-06
Thanks, this is super helpful. I didn't know about that feature of the SVE instructions. I was curious and it looks like RISC-V takes it a step further even and is "Vector Length Agnostic"[1]. Pretty cool!
[1]: https://gms.tf/riscv-vector.html
jakeogh · 2022-02-08
I checked https://NN-512.com and gituhb, trying to grok.
reading: https://gms.tf/riscv-vector.html
VLA (vector length agnostic) indirection makes the execution harder to control?
So... RISC-V does not provide instructions for each exponent
MMX(64), SSE(128), AVX(256), AVX512(512)
and therefore the the compiler/assembler/human needs to use the input-length-agnostic instructions which the hardware lowers to operations that are implementation specific?
twic · 2021-08-17
RISC-V has a solution to this which seems quite elegant - the vector length is set by the program, up to some maximum, and for the final block, it is simply whatever is left:
https://gms.tf/riscv-vector.html
monocasa · 2020-09-05
> That doesn't make sense --- how would the code know how much to increment pointers by, how many times to loop, alignment, etc. ?
You ask the hardware. The current vector width is a register that can be set and queried.
https://gms.tf/riscv-vector.html
pantalaimon · 2020-08-06
RISC-V is also adding Vector extensions.
The cool thing about those is that they are variable length, so code can take advantage of newer hardware / degrade gracefully on less capable one.
https://gms.tf/riscv-vector.html