Fabricated Knowledge

This blog has been very helpful to follow the recent trends and players from an investors standpoint - https://www.fabricatedknowledge.com

"Most large investors vote alongside Glass Lewis and ISS recommendations, the two most prominent proxy solutions for investors. Most GL/ISS recommendations tend to vote with the board and don’t change much unless something drastic happens. If you’re a passive investor, you vote in line with the two proxy powerhouses." - The Death of Intel: When Boards Fail https://www.fabricatedknowledge.com/p/the-death-of-intel-when-boards-f…

Ben Thompson and Doug O'Laughlin ( https://stratechery.com/2025/the-oracle-inflection-point-apples-price-… (paywall), https://www.fabricatedknowledge.com/p/capital-cycles-and-ai ) are calling it a bubble, largely because we've entered the cycle where cash flows aren't paying for it, but debt is (See Oracle. they won't be able to pay for their investment with cash flow). I think even Byrne Hobart would agree (from his interview with Ben): -- Bubbles are this weird financial phenomenon where asset prices move in a way that does not seem justified by economic fundamentals. A lot of money pours into some industry, a lot of stuff gets built, and usually too much of it gets built and a bunch of people lose their shirts and a lot of very smart, sophisticated people are involved with the beginning, a lot of those people are selling at the peak, and a lot of people who are buying at the peak are less smart, less sophisticated, but they’ve been kind of taken in by the vibe and they’re buying at the wrong time and they lose their shirts, and that’s really bad. -- This is a classic bubble. It starts, builds, and ends the same way. The technology is valuable, but it gets overbought/overproduced. Still no telling when it may pop, but remember asset values across many categories are rich right now and this could hurt.

> AI models do not need coherent memory, the access pattern is regular enough that you can make do with explicit barriers. response to both this and the sibling: even for training, I remember some speculation that explicit synchronization might not even be needed, especially in the middle stages of training (past the early part, before fine tuning). it's not "correct" but the gradient descent will eventually fix it anyway, as long as the error signal doesn't exceed the rate of gradient descent. And "error signal" here isn't just the noise itself but the error in gradient descent caused by incorrect sync - if the average delta in the descent is very slow, so is the amount of error it introduces, right? actually iirc there was some thought that the noise might help bounce the model out of local optimums. little bit of a Simulated Annealing idea there. > The bigger problem is that by the time PCIe 7.0 will be actually available, 242GB/s per direction will probably not be sufficient for anything interesting. yea it's this - SemiAnalysis/Dylan Patel actually has been doing some great pieces on this. background: networks really don't scale past about 8-16 nodes. 8 is a hypercube, that's easy. You can do 16 with ringbus or xy-grid arrangements (although I don't think xy-grid has proven satisfactory for anything except systolic arrays imo). But as you increase the number of nodes past 8, link count blows out tremendously, bisection bandwidth stagnates, worst-case…

According to the graph on the linked page below, the cost per transistor hit a minimum at 28nm (which was the last of the planar designs), and has risen slightly with FinFET (which is not as reliable as planar). "The chart below is from Marvell’s 2020 investor day. The bar for 28nm was approximately 2011-2012." Cost is per 100 million gates. 90nm - $4.01 65nm - $2.82 45/50nm - $1.94 28nm - $1.30 20nm - $1.42 16/14nm - $1.43 10nm - $1.45 7nm - $1.52 https://www.fabricatedknowledge.com/p/the-rising-tide-of-semiconductor

It depends how literally one wants to take the law. The "law" is doubling density every two years. So strictly speaking it is done because it has taken longer than two years. But if you choose the looser interpretation and simple read it as, transistor density increases with time, then it's not dead. Probably the bigger deal is cost per transistor is actually going up with the new nodes. https://www.fabricatedknowledge.com/p/the-rising-tide-of-semiconductor… and https://www.eetimes.com/moores-law-dead-by-2022-expert-says/

Maybe, but it worked out really well last time we did this. I say the government ended up with a tremendous ROI. https://www.fabricatedknowledge.com/p/history-lesson-the-1980s-semicon… What about the safeguards, which are in place, makes you uneasy?

> CPU heat output is limited by the resistance of the semiconductors. This is not true anymore. At leading edge process nodes (i.e., smaller conductor pitch), the bulk resistivity of copper changes dramatically because it is increasingly dominated by ballistic electron scattering on the interfaces and grain boundaries: surface area has decreased as a fraction of volume and the average grain size has shrunk to fit inside the interconnect lines. Alternative metals like Cobalt and Ruthenium have been proposed and to some extent used in production as an alternative to Cu for the low interconnect layers, but they just arrest the trend -- the fact is that the interconnect resistance is much higher than it used to be. It's also why a lot of the big players like TSMC and Intel are investing heavily in backside power delivery. Here is an accessible article on the topic: https://www.fabricatedknowledge.com/p/backside-power-delivery-and-bold (Also: high-voltage DC power is commonly used for long-range transmission and does not have coupling issues)

We really lack a better name here than packaging. When it was packaging substrate, wire-bonds, chip, pins, and heat spreader, yeah, ok. But now the substrate is probably it's own interposer, perhaps with more interposers in it, the chip is probably at least two chips, when more and more is stacked together & intricately interconnected: the word packaging feels super super insufficient. Massive shout out to "The Rising Tide of Semi-conductor Costs"[1] for talking to a bunch of related concerns. It didn't go nearly deep enough into this point, and this article does a little more, but it found the choice quote, and it's implicitly about "all this": > ASML, in its investor day, made a bold statement that Moore’s Law will continue with system-level scaling. Which seems exactly so. Via "advanced packaging". Via stacking more chips up. Via better interposers & EIMB to string together more chips more closely. We're on the cusp of advanced chips becoming many chips. For places like flash memory, this has been the way already for a while, but we're stacking cache and main memory and real compute atop each other, connecting them side ways-- what was "the chip" is being reborn, is now a system of chips. However the Rising Tide article's core point is much more complex, about costs & complexity. It could well be blistering correct that this reformulation, that this advanced packaging, while allowing much more advanced scaling, wont aid the same Moore's Law we have come to enjoy: >…