Electron Update

For some perspective, check electronupdate's recent 'decapping': http://electronupdate.blogspot.com.au/2016/10/decap-of-cell-phone-sim-… It is not just a little block of secure RAM labelled a 'smartcard'. It contains as much CPU as a low end phone. Amazing.

There was a Leviton (well known brand) timer power switch that would prematurely fail. They spec’d out too low temperature rating of a capacitor that was right next to a heat source and cook itself to death: https://m.youtube.com/watch?time_continue=315&v=BQM4ERy-wpY https://electronupdate.blogspot.com/2017/12/leviton-ltb30-buzzing-time… So yeah, tried too hard to save 2 cents

Why would you need to sign an NDA? There are decaps readily available. The ESP32 a separate die for the flash memory, but everything but the flash is on a single die, which sounds like a SoC to me (The definition of SoC devices have always included devices with off-die RAM and Flash). These aren't "a bunch of components on printed circuit boards" as you initially claimed. https://electronupdate.blogspot.com/2018/08/espressif-esp32-teardown.h…

Is this done physically/electrically? Echo devices, for example, were sold as having a "hardware mute switch" from day one. Sure enough, teardown after teardown[0] has confirmed the hardware mute switch actually physically disables the mic (cuts power to the ADC, mic lines, etc). If this is implemented in software it's no different than a phone and worse than an Echo. [0] - https://electronupdate.blogspot.com/2021/01/amazon-echo-flex-microphon…

The reason could be the same as given in the other RPi post today (about the Pi Zero 2W): > The black rectangle is a "bare-die soldered bumped package"... what that means is the silicon die has no black epoxy covering. A metal layer is deposited on the die and then solder bumps attached which allow the part to be soldered to a PCB. The reason for this, is as expected, cost. No package (epoxy, substrate)... no cost. One sees this more-and more with electronic assemblies. > The only downside is that external light can actually affect the chip operation (light hitting the die releases electrons at PN junctions creating errors in circuit operation ) .. .however here the Faraday metal shield helps prevent this. http://electronupdate.blogspot.com/2021/11/raspberry-pi-zero-2w-what-d…

I've been interested in how 4-function calculators and cheap clocks work for a while. Most of the implementational details would appear to be buried in files on engineering workstations at Chinese factories. I found a calculator teardown at http://electronupdate.blogspot.com.au/2016/08/reverse-engineering-simp… a while ago. The author says it's very old but doesn't provide a ballpark (eg, 1990, 1995, 1998, 2003, etc). It does look quite hairy (and possibly not particularly compactly designed?). I would guess there's a ridiculously simple ALU somewhere in there, but I wonder what else is involved in the specific context of a high-production-volume fixed-functionality design. I hope to find something similar for a clock at some point.

My first impression is that the RPi foundation has finally jumped the shark. There is a vast, vast number of microcontrollers available in every possible configuration. How can this chip possibly differentiate? How is custom silicon necessary to make a microcontroller dev board? How does this support their educational mission? I'm starting to come around. The chip is interesting: it's as if they were listening to my (silent) complaints about the microcontroller industry. Dual core micros exist but dual core, low end, low power is more unique. Having multiple cores can actually simplify firmware since you can dedicate a core to a polling event loop rather than having to design, configure, and debug an interrupt based state machine within the hardware's limitations. The PIO peripherals are very interesting as well and look like a lot of fun. These two features are a half step towards something like the Parallax Propeller. The on board peripherals don't begin to approach the vast quantity and complexity that other manufacturers have accumulated over the years, but the PIO and extra core help to overcome this. The peripheral to GPIO mapping is not quite any-to-any but it is very flexible. The pinout was specifically designed to be easily and logically broken out on a single layer. These issues are near to my heart since I'm in process of fighting to work around ST's almost random pin assignment and inflexible GPIO alternate functions on a much larger chip. ST does seem to be…