OneZero Debugger

>1. Always sad for me to know how much popular are wireless chargers, wasting 47% more energy aprox for charging the same as a wired charger. https://debugger.medium.com/wireless-charging-is-a-disaster-... (too much catastrophic conclusions in this article but that percentage is real, you could check it in another tests, articles, whatever ..) The percentage value looks bad but how much is that in absolute terms? Using the figures from the article, wireless charging uses 6.75 Wh more per full charge. Assuming you charge that much every day, that's 2.46 kWh per year, or 42 cents at average US electricity prices[1]. I think that's a price worth paying for the convenience. [1] https://www.bls.gov/regions/midwest/data/averageenergyprices_selecteda…

Here's two great examples of the standard's ineffectiveness https://news.ycombinator.com/item?id=10508494 https://debugger.medium.com/usb-c-was-supposed-to-simplify-our-lives-i… Apple has stringent regular testing standards on MFI certified cables - they regularly buy them up "in secret" to continuously test that they're meeting cert requirements. If memory serves, the contract stipulates Apple can levy massive penalties for "bait and switching" actual certified cables with inferior product. When the Nintendo Switch came out, Nintendo, being Nintendo, wired the USB-C adapter not to spec, so you'd need a Nintendo power brick to charge the thing. This lead to people trying to use the Nintendo charger on other devices (because USB-C looks like USB-C) and frying them/ blowing them up.

wireless charging efficiency isn't too great either https://debugger.medium.com/wireless-charging-is-a-disaster-waiting-to…

Isn't it because it is a SoC? I found the following article enlightening: https://screenrant.com/apple-silicon-m1-mac-macbook-chip-soc-explained… Edit: ignore that previous link, way better is the one mentioned by another poster: https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2

1. Always sad for me to know how much popular are wireless chargers, wasting 47% more energy aprox for charging the same as a wired charger. https://debugger.medium.com/wireless-charging-is-a-disaster-waiting-to… (too much catastrophic conclusions in this article but that percentage is real, you could check it in another tests, articles, whatever ..) 2. Totally agree with that, if camera is fundamental for you maybe not the right choice. 3. They also take compromises to have an ethical production, try to guarantee there is no exploitation as much as they could, from the extraction of mineral, manufacturing ... (they didn't do it for all, but they are advancing as far as they could, also with all existing certifications for that, so it's normal that is expensive. So our choice to value that things, if we could afford it, or not.

On average it takes about double the power to charge the device. Coils aren't always properly aligned, and it's not as efficient in the first place. If we adopt this tech en masse, we'll need to build some more power plants. https://debugger.medium.com/wireless-charging-is-a-disaster-waiting-to…

Wireless charging can not even approach the speeds of wired charges and your energy estimates are off. https://debugger.medium.com/wireless-charging-is-a-disaster-waiting-to…

No doubt they would have made a faster x86 CPU. But how would this CPU compare to M1? M1 superiority must have something to do with ARM's fixed instruction length according to this article: https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2

Not the same thing but related: https://debugger.medium.com/a-search-engine-that-finds-you-weird-old-b…

Not exactly what you are asking for. But I have this project in my todo list. The Very Slow Movie Player: https://debugger.medium.com/how-to-build-a-very-slow-movie-player-in-2… It needs to be built/assembled yourself, however there aren't that many parts involved

In his 2020 article about wireless charging inefficiency [0], Eric Ravenscraft wrote: > In my tests, I found that wireless charging used, on average, around 47% more power than a cable. [0]: https://debugger.medium.com/wireless-charging-is-a-disaster-waiting-to…

For the most part, I think it's mostly (but not all!) the same, where the hype and excitement is from a new generation of VCs and founders who didn't experience the VRML/second-life era. Of course, not only is the technology to facilitate a metaverse is better, but I think society has also evolved a lot since then. Remote work/life is now much more of a mainstream/accepted thing than it used to be. Internet is now a mainstream full-blown appendage via our smartphones. I'm much more optimistic a metaverse (in a Platonic ideal sense) could catch on this time around, BUT I'm much less sure that what will be hawked to us is the "right thing" (whatever that means). I do think this article posted on HN last week is definitely onto something that Meta and other attempts may not be thinking about. https://debugger.medium.com/the-metaverse-is-already-here-its-minecraf…

This article is a bit sensationalist, but they claim to have gotten mid-60s efficiency [1]. I think I misread them initially when they said "47% more power" - I took that to mean 47% efficiency, but on re-reading it's closer to 66%. My bad! [1] https://debugger.medium.com/wireless-charging-is-a-disaster-waiting-to…

You are not alone in this. https://debugger.medium.com/tech-savvy-readers-are-designing-their-own…

Wireless loses 1/3 of the energy. It requires 47% more energy, and even more when misaligned. https://debugger.medium.com/wireless-charging-is-a-disaster-waiting-to…

> "Why? Somehow Apple's chips will get better, but competition will stand still?" Arguably this has been the case for the last ten years (comparing chips on iPhones to others). I think x86 can't compete, CISC can't compete with RISC because of problems inherent to CISC (https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2… It won't be for lack of trying - x86 will hold them back. I suppose in theory they could recognize this e-risk, and throw themselves at coming up with a competitive RISC chip design while also somehow overcoming the integration disadvantages they face. If they were smart enough to do this, they would have done it already. I'd bet against them (and I am).

I'm not sure that's entirely true. According to this (see "Why can’t Intel and AMD add more instruction decoders?"): https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2 ..a big part of the reason the M1 is so fast is the large reorder buffer, which is enabled by the fact that arm instructions are all the same size, which makes parallel instruction decoding far easier. Because x86 instructions are variable length, the processor has to do some amount of work to even find out where the next instruction starts, and I can see how it would be difficult to do that work in parallel, especially compared to an architecture with a fixed instruction size.

> * It's much more irregular to decode than other instruction sets/IRs According to this blog post, it's not just "much more irregular to decode", instruction deciding is the Achilles Heel of x86 which allows M1 to be so fast by comparison. https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2

This article discuss exactly what you are talking about and why it is not an issue: https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2

There was an article posted not long ago that suggested the variable length instruction set in x86 chips prevented some of M1's most important design innovations being replicated by Intel and AMD. https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2

This article might help the picture come into focus a little better: https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2

Here's a really good article describing why the M1 chip is so fast. Tl;dr it's a beefy CPU with a massive reorder buffer, and a bunch of discrete subsystems (gpu, ml core, dsp, etc). https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2

Saying it can process twice as many instructions per clock cycle is an incredibly incorrect statement. It's not as incredibly incorrect as you may think. An x86 instruction can be as big as 15 bytes and there's no easy way for the decoder to know where one instruction ends and the next one begins. All ARM instructions are one size, making instruction decoding more efficient and makes out of order processing faster as well. More details at https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2

https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2 One more article going into it. Better out of order execution seeming to be a big one.

Having the same instruction set doesn’t imply that the same sequence of instructions as before will be optimal. If so, Apple telling them which formerly optimal sequences now have better replacements would help. Also, do we know their new CPU is pure ARM64, and doesn’t have any Apple-specific extensions? I may not have looked hard enough, but can’t find any statement about that on developer.apple.com. Edit (after reading https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2… Apple probably also knows when it makes sense to offload some code from golang’s standard library to one of pieces of specialized silicon on the M1.

This article gives a pretty good overview of the components that make the M1 different (nb. I'm not a hardware person): https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2

Far from "like I'm 5", but here is a technical explanation: https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2

On the other hand, this just came out a few days ago: https://debugger.medium.com/apples-new-iphone-is-far-from-green-1803f4… This discussion also just came up 2 days ago: https://news.ycombinator.com/item?id=24911413

ARM is RISC , Intel and AMD are CISC, One important reason is their new pipelining facility. Apple M1 has 16 units that can pipeline their instructions. Meaning, they can reorder sequential instructions that aren't dependent on each other to run in parallel. That is not threads or anything, that can be and is being done in a single threaded program. AMD and Intel have 4 units for reordering tops, because their architecture is CISC and on instruction can be up to 15 bytes. M1 is RISC and instructions are just 4 byte fixed-length. Thus architecturally it is easier to reorder instructions for RISC than CISC. CISC were better because of the specific instructions but now Apple has stuffed their CPU with specific hardware for alot of things including machine learning, graphic processor and encryption, instead of specific instructions, Apple has specific hardware, and can do with less instructions. And since they control hardware, software SDKs and OS they can actually get away with such radical changes. Intel and others can't, without a big change in industry. Source: https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2