Clifford Wolf

The term "formally verified" could be misleading. Some people assume it means "100% bug free". Whenever someone claims something is formlally verified one should ask what properties were verified exactly. In this work the approach they use (bounded model checking) could find some bugs on a subset of RISCV archictecure they formalized. I recommend looking at their slides for better understanding of the scope of the work: http://www.clifford.at/papers/2017/riscv-formal/slides.pdf Nevertheless it is definetely a very impressive work and pracrically useful.

Not the author, but my advice would be to grab a cheap devboard and try doing something, anything. My approach was to implement very simple interfaces without using libraries. Simulators are nice and all, but you won't feel the magic with these. There's many cheap options[0] these days, but I'd suggest something based on iCE40[1], as they are cheap and have the most mature support in the open stack thanks to icestorm[2]. Excellent, dirt-cheap options include icestick, tinyfpga bx and blackice mx. These are all <$70. [0]: https://joelw.id.au/FPGA/CheapFPGADevelopmentBoards [1]: https://en.wikipedia.org/wiki/ICE_(FPGA)#iCE40_(40_nm) [2]: http://www.clifford.at/icestorm/

>Thanks, the damage was and is pretty bad- and long-lasting. But, "be like water" and all that. I'm slowly pivoting to hardware development. Studying welding and CNC operations now also. Keep at it, you are setting an amazing example here. Very good luck with it all. edit - if you are pivoting to hardware development, get one of these; http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/iCE40H… use this on it; http://www.clifford.at/icestorm/ and this is where you can find some useful modules - https://opencores.org/ Is some of the most fun I have had in ages in making tech do weird shit. I currently have a stepper motor rumnning over optic fibre as the first stage of my new 3d printer build.

The IceStorm tools are open source, based on the reverse-engineered Lattice iCE40 FPGA architecture: http://www.clifford.at/icestorm/ I found it very easy to get started, although first you have to buy a compatible FPGA (iCEstick etc.) and make an adapter for your preferred output device. The advantage of the MISTer is that you have all the connectors, FPGA cores for popular platforms and a couple of ARMs for when things get complicated. Raspberry PI is fine, but not great for latency, assuming you need that extra 1/60 second. (HDMI monitors add so much latency though!) Some folks have had success connecting PIs to old CRTs though.

I haven't checked up on the project in a while, but http://www.clifford.at/yosys/ has an interesting open source toolset. It's been a while since I've done much with FPGAs as they're not that friendly to hobbyists compared to analog circuitry and microcontroller based digital circuitry, though they're still interesting to handle. My general recommendation is to try to get to the point that you can sell one circuit board (populated or unpopulated) as (depending upon your skill level) it may highlight areas that you can learn more as well as providing a portfolio piece.

For some context this is a very popular and cheap series of FPGA devices. For example you can buy the Arty board which has one of these FPGAs for $99 (https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-f… or the slightly more advanced Nexys 4 DDR for $265 (https://store.digilentinc.com/nexys-4-ddr-artix-7-fpga-trainer-board-r… Currently you must use the Xilinx Vivado tool which is a 40 GB download [no, that isn't a typo], requires a paid license to unlock the full features, and is generally awful to use. This work should eventually lead to a complete open source toolchain to program these devices, just like Project IceStore for the Lattice devices (http://www.clifford.at/icestorm/ https://rwmj.wordpress.com/2018/03/17/playing-with-picorv32-on-the-ice…

I have an iCEstick sitting in a drawer, for which some pretty amazing open source tools are available: http://www.clifford.at/icestorm/ I wish I had the time to play with it!

Just a shout-out about the Icestorm project which provides a complete open-source toolchain for Lattice's iCE40 FPGAs. It's mostly the work of one guy (Clifford Wolf): http://www.clifford.at/icestorm/. It's worth noting that arachne-pnr (https://github.com/cseed/arachne-pnr) is written by a different person (Cotton Seed).

Yeah, what stops me usualy plonking one in my project is the 20GB of IDE I'll have to install to have the pleasure of seeing it take /forever/ to do it's thing. However this has just changed. There is an excellent project at http://www.clifford.at/icestorm/ that has reversed the format for a series of the Lattice FPGA and provide an open source end-to-end solution... And AFAIK they haven't been told off for doing so. I therefore have one of their USB stick evaluation board on my desk to have a play with as soon as I can. They also have 'hacker friendly' packages.

newsbeuter author here. If you want to develop your own text terminal tools, I can really recommend STFL: http://www.clifford.at/stfl/ Without it, I would have probably been driven crazy when I attempted to put together a UI. It helped me get from an idea to a working prototype really quickly. In the case of newsbeuter, like 2 days.

I'm on my first foray into FPGA development, using IceStorm as the toolchain for a Lattice iCE40 FPGA (iCE40HX4K) to implement a system controller for my homebrew 6502 single board computer. The FPGA is (work in progress) doing clock management, address decoding, memory bank switching, SPI comms, some GPIO, and bootstrap to RAM from SPI flash memory. It's fantastic having an open-source toolchain! It's why I chose the Lattice iCE40, and perhaps what got me over the line to even try FPGA development; the closed proprietary tools are very off-putting to new starters. I had previously dabbled with a Xilinx FPGA dev board, but spent most of my time battling the giant Xilinx ISE toolchain. Big thanks to Claire Wolf for creating IceStorm and making FPGA dev more accessible to software engineering types like me. Aside (cc: dang?) I think http://bygone.clairexen.net/icestorm/ is the newer/better canonical URL for IceStorm, since the creator changed their name, as linked to from their projects page at https://www.clairexen.net/projects and mentioned at the bottom of the current http://www.clifford.at/icestorm/ page.

> However, if this initiative takes off, it'll be a big help in creating an open source EDA toolchain community. The opensource EDA toolchain community is already producing some good stuff, Symbiflow: https://symbiflow.github.io/ is a good example, it's an open source FPGA flow targeting multiple devices. It uses Yosys (http://www.clifford.at/yosys/) as a synthesis tool which is also used by the OpenROAD flow: https://github.com/The-OpenROAD-Project/OpenROAD-flow which aims to give push-button RTL to GDS (i.e. take you from Verilog, which is one of the main languages used in hardware to the thing you give to the foundry as a design for them to produce). The Skywater PDK is a great development, which is a key part of a healthy opensource EDA ecosystem though there's plenty of other great developments happening in parallel with it you will note there's some people who are involved in several of these projects they're not all being developed in isolation. The next set of talks on the Skywater PDK include how OpenROAD can be used to target Skywater: https://fossi-foundation.org/dial-up/

You should not use AWS F1 instances if you are just starting out. They will burn a nice-sized hole in your wallet and the only thing you'll get in return is confusion and frustration as a beginner. The AWS F1 devkit and APIs are largely oriented around making OpenCL-based designs easy and fast to develop (using Xilinx's "SDAccel" framework), but if you're just starting out you almost certainly want to start with classic RTL development using Verilog or whatnot. But "traditional" RTL development is substantially more involved. The documentation and the environment itself is largely oriented with the assumption you're a semi-experienced RTL developer and there's no real way around that part. (For example, even when using OpenCL, you're going to have a hell of a time optimizing anything without understanding real RTL/digital design principles.) The F1 also has a non-trivial build system, meaning you have to do literally everything on AWS. Not a deal-breaker, but considering the equivalent of a "Hello World" will take you something like 30+ minutes to compile using something like a t2.2xlarge, and anything beyond that will be multi-hour (yes, this isn't an exaggeration) -- you probably don't want to just be spending money on every minor iteration. I would suggest getting a cheap Lattice FPGA and using Project Icestorm, which is a free FOSS Verilog toolchain, in order to get started. This will cost you closer to $20 USD. https://www.latticesemi.com/icestick and…

Regarding the ASIC part: There are several good courses online that explain the whole process from hardware description in a hardware description language to GDSII file, which you could send to a foundry in some detail. See for example this course https://web.csl.cornell.edu/courses/ece5745/, there are also very good courses available from Berkeley and MIT. What is usually missing is the more gory details of the backend flow, which can become very involved and complicated depending on your design and process. Unfortunately someone who has no access to the EDA tools by cadence / synopsis or standard library files from foundries, cannot really follow along all that far, you are limited to working at the RTL level. There are several good open source RTL simulators available, I have personally used mostly verilator, which supports (almost) all synthesizable constructs of system verilog and has performance close to the best commercial simulators like vcs. It compiles your design to C++ code which you can then wrap in any way you like. You should also check out https://chisel.eecs.berkeley.edu/, which is a hardware description language embedded in scala, the nice thing about it is that it has a relatively large number of high quality open source examples, designs (https://github.com/freechipsproject/rocket-chip) and a library of standard components available, something which can't really be said of verilog / vhdl unfortunately. As an added bonus you can actually use IntelliJ as…

No - it's the massive investment in tooling. I see comments like these all the time about 'open source bitstream generators' and whatnot. If you have a very simple, regular architecture, then P&R (place & route) is relatively simple, and has been done (there is an open-source bitstream generator for the Lattice iCE40 chips, see http://www.clifford.at/icestorm/). This line from that page in particular: "It has a very minimalistic architecture with a very regular structure. " For anything close to a modern FPGA, the P&R is only the start of the problem - timing is the next big one. Having a large design not meet timing can be a nightmare, but the tools take delay (extracted from the design) into account for routing, so you'd have to add that; also, I think the amount of effort to get the "hard macros"/specialized in-silicon blocks configured correctly would be amazing. You'll notice that even in the iceSTORM project, PLL's and timing analysis are not yet implemented. I use the Xilinx Zynqs at work, and they contain high speed serdes, dual-core ARM processors, and a boatload of other items. There are large teams who are employed full-time, and frequently get their Masters/PhD with a specialty in VLSI/EDA, developing these algorithms, testing them extensively, and then implementing them. With the money someone like Xilinx brings to the table, they can pick those individuals out from school directly. It isn't a CPU, and it never will be. I'm amazed at what free software can…

i didn't mean to nitpick and it's not nitpicky since there are now open toolchains (though not for xilinx) that you support verilog as a frontend http://www.clifford.at/yosys/ http://www.clifford.at/icestorm/

https://clash-lang.org/ http://www.clifford.at/yosys/ I am hoping we can start proving many if the things they brute-force model check today, too.

This is a long standing problem - it applied to microcontrollers 2 decades ago as well. There are people trying to solve this problem - have you seen IceStorm for Lattice for example: http://www.clifford.at/icestorm/ Fortunately microprocessors these days are supported by lots of toolchains, so let's hope FPGAs will get there too.

>The rest of this page explains how to compile and install a "bitstream" file to implement this processor in a cheap (about $50) FPGA board, then how to build Linux for that board and boot it to a shell prompt. >Numato: The cheapest usable FPGA development board ($50 US) the j2 build system currently targets is the Numato Mimas v2 (also available on amazon). It contains a Xlinux "Spartan 6" LX9 FPGA that can run a J2 at 50mhz, 64 megs of SDRAM, USB2 mini-B, and a micro-sd card slot. PDS: Nice! But, it would be an additional serious "would be nice"(!) -- if this could run on Lattice FPGA's / IceStorm Open Source Toolchain: https://www.latticesemi.com/Products http://www.clifford.at/icestorm/ https://github.com/YosysHQ/icestorm

SystemVerilog has several useful additions for FPGA engineers, but tool support has been slow to materialise. For the moment, I’ve kept to the few features that Xilinx Vivado and Yosys http://www.clifford.at/yosys/ are both happy with, such as enums, logic data type, and always_ff etc. I’ve not used VHDL in anger, so can’t give you a useful opinion there.

yosys with yosys show command can do it for Verilog: http://www.clifford.at/yosys/files/yosys_appnote_011_design_investigat… I found it really helpful to see what a chunk of Verilog code would look like after synthesis. There is an online version at here: http://www.clifford.at/yosys/nogit/YosysJS/snapshot/demo02.html which uses YosysJS. Hopefully someone can port Compiler Explorer UI to this

Gowin might just fill this niche. They are working with yosys on open source support as well. https://www.gowinsemi.com/en/product/detail/2/ http://www.clifford.at/yosys/cmd_synth_gowin.html

This FPGA is not open source by design, but this project seems fairly complete: http://www.clifford.at/icestorm/ "Project IceStorm aims at documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files." Lattice (the FPGA's manufacturer) seems open-minded regarding such efforts: https://twitter.com/latticesemi/status/1269115302140231682

This is not the case for the FPGAs targeted here. Encryption is optional on Xilinx 7-Series. Also there already is an open source toolchain coming up for them. http://www.clifford.at/yosys/

Is there any way that the breaking of the Xlinix bitstream encryption opens the door to documenting and reverse engineering that bitstream in the same way that was done with Project IceStorm[0] for the Lattice iCE40 FPGAs? [0] Project IceStorm - http://www.clifford.at/icestorm/

How hard would it be to use Yosys (http://www.clifford.at/yosys/documentation.html) for logical gate synthesis to run arbitrary Verilog on TFHE?

> There is no synthesis engine for VHDL in it that I'm aware of. The answer is one simply Google search away: http://www.clifford.at/yosys/cmd_verific.html The commercial version of Symbiyosys uses Verific to parse and elaborate designs. The Verific front-end supports Verilog, SystemVerilog and VHDL. When it comes to formal verification, the Verific front-end and the Yosys Verific backend support a large set of the formal verification primitives of SystemVerilog. (See also the above link.)

Verilator is an awesome tool. I suggest if you are interested in open-source EDA this you also check out Icarus Verilog [1] - an event based Verilog sim, Yosys [2] - a Verilog synthesis tool and formal solver, and NextPNR [3] - a place-and-route tool. The set of these provide a pretty reasonable set of tools for developing hardware (that is HDL) with fully open source software! [1] - http://iverilog.icarus.com/ [2] - http://www.clifford.at/yosys/ [3] - https://github.com/YosysHQ/nextpnr

Have you seen Project IceStorm? I don't know if ICE40 FPGAs would be good fit here, but they could definitely be more hobbyist friendly. http://www.clifford.at/icestorm/

you can try the (~$15) upduino 2.0[0]. it's supported out of the box by the free (OSS) icestorm toolchain[1]. The upduino board itself is also OSS. [0]: http://www.gnarlygrey.com [1]: http://www.clifford.at/icestorm/