Stuffedcow

For those interested in the number of physical registers on a modern CPU, Henry Wong and Travis Downs have done some great work deducing the physical implementation of recent Intel cores: https://travisdowns.github.io/blog/2019/06/11/speed-limits.html#ooo-ta… http://blog.stuffedcow.net/2013/05/measuring-rob-capacity/ https://travisdowns.github.io/blog/2019/12/05/kreg-facts.html https://travisdowns.github.io/blog/2020/05/26/kreg2.html

I wish the author would have been more specific about the processor being tested. This is the sort of thing that is extremely dependent on the microarchitecture of processor used. I wonder if he's testing on AMD or older Intel? Modern Intel chips usually do an very good job of "store-to-load forwarding" when the load is the same size or smaller than the store. Although it's testing a slightly different effect, this is a great recent article on the topic: http://blog.stuffedcow.net/2014/01/x86-memory-disambiguation/

I wonder why PC floppies didnt switch to ZBR https://en.wikipedia.org/wiki/Zone_bit_recording at some point to beef up storage capacity. Chuck Peddle of 6502 fame did a PC in the eighties called Victor 9000 https://en.wikipedia.org/wiki/Sirius_Systems_Technology#Victor_9000_/_… where he implemented special software driven (6502 controller just like in Commodore drives) ZCLV/GCR floppy drives. 1.2 MB using ordinary 5.25 DSDD disks (500/360 KB capacity in PC). 100% capacity gain from switching to 80 tracks, another 50% on top of that due to ZCLV/GCR. Standard PC 1440KB 3.5 inch HD floppy using same strategy would start at 2160KB. There is this great "Discovering Hard Disk Physical Geometry through Microbenchmarking" blog post by Henry Wong visualizing whats going on on the platters https://blog.stuffedcow.net/2019/09/hard-disk-geometry-microbenchmarki… Whats crazy to me is learning early HDDs didnt use ZBR either, manufacturers were leaving 50% capacity gain on the floor. 1989 Seagate ST157a is comparable to HD floppy, denser tracks at 650 vs 135 tpi, but almost two times lower Bit density :o 10000 vs 17434 bpi. ST157a could lose one platter, or gain half capacity 40->60MB by going with a little bit more complicated ZBR controller (switching bitrate per track).

> - call/return address mismatch Definitely, it's as important as ever. If you have matched call/ret pairs but cause an address mismatch by say modifying the return value on the stack, the subsequent `ret` will mispredict. OTOH, if you cause a mismatch by having unbalanced call ret pairs, e.g., a `call` to a location that does a `jmp` back instead of a ret, the situation is much worse: the ret prediction stack is mismatched so you'll can mispredict on the next N return calls where N is 16 or 32 or whatever the size of the stack is (it doesn't mean that will happen: if the following code does many more calls before the correspond rets the bad predictions may fall of the stack and never be used). The good news is that this one is really easy to avoid. Why would you end up with mismatched call/ret in the first place? It doesn't happen in normal code and even in hand-rolled assembly I can't see many reasons you'd end up like that. There is one pattern that is used sometimes with mismatched calls: `call; pop eax` to get the current IP in rax (for example) - useful in 32-bit position independent code (in 64-bit code you can just use rip-relative addressing). This one is special cased though so it does not cause a misprediction. Way more details avaialble here (this page is also linked in my post): http://blog.stuffedcow.net/2018/04/ras-microbenchmarks > - mixing int/float vector instructions with same register These are the so-called domain bypass penalties. They are much…

Note that they don't: https://blog.stuffedcow.net/2015/08/win9x-tlb-invalidation-bug/

Running or virtualizing DOS-era software can be non-trivial: see, for example, Windows 98 vs TLB cache invalidation behavior in modern CPUs https://blog.stuffedcow.net/2015/08/win9x-tlb-invalidation-bug/ requiring a patch. Any code that does loop counting to estimate cycles for sleep() will also overflow (hello, Pascal CRT Error 200!) requiring a different patch.

> perhaps the rail could shift a millimetre or so back and forth to allow micron-fine positioning from a milimeter-course array of heads. You're talking in terms of millimeters and microns. That is roughly the scale that CDs operated at. According to https://blog.stuffedcow.net/2019/09/hard-disk-geometry-microbenchmarki… > In the newest drive I have, average track pitch is 80 nm and an average bit is 17 nm in length. That's for hard drives providing 1TB per (double-sided) platter, less than half the density of today's most advanced hard drives.

A patch is available [0] to allow Windows 98 to be virtualized on more modern CPUs including Ryzen CPUs. It patches the "TLB Invalidation Bug". [1] [0] https://github.com/JHRobotics/patcher9x [1] https://blog.stuffedcow.net/2015/08/win9x-tlb-invalidation-bug/

That sounds like this bug, of which someone created a patch for (look at the end of the comments): https://blog.stuffedcow.net/2015/08/win9x-tlb-invalidation-bug/ Turning off nested paging seems to work around it.

Very cool. Other similar and interesting non-LRU caches: MySQL https://medium.com/@arpitbhayani/what-makes-mysql-lru-cache-scan-resis… Intel Sandy Bridge+ https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/

These graphs look linear to you? https://blog.stuffedcow.net/2012/07/ivy-bridge-power-consumption/ https://qph.cf2.quoracdn.net/main-qimg-61820a6b86759c354d41dbbd16a0385…

I see how it worked. That measurement uses the 2013 technique published by Henry Wong. I think it’s probably a reasonable estimate of the instruction window length but to say that’s the same as the buffer size is making a number of architectural assumptions that I haven’t seen any evidence to justify. I suppose in the end it doesn’t really matter as users of the chip though. http://blog.stuffedcow.net/2013/05/measuring-rob-capacity/

I think it does not matter, skipping means the CPU does not execute it, but it still has room in RoB which is enough for defending Spectre. see this article: http://blog.stuffedcow.net/2013/05/measuring-rob-capacity/

You (and a lot of people) make it sound like its magic but it's not - http://blog.stuffedcow.net/2014/01/x86-memory-disambiguation/