Adapteva Blog

Good that they're getting on the bandwagon as they're already popular with maker types. I also like the serendipity where this post led me to an equally exciting one: http://www.adapteva.com/announcements/an-open-source-8gbps-low-latency… Love that they developed and open-sourced a 8Gbps, 1us, I/O interface. That might come in handy. :)

I don't know how practical that is; FPGAs are very efficient, but they won't come close to the raw computational power of a GPU. Many moons ago, the dream was to have a configurable FPGA in every computer, but GPUs ended up winning out due to games, among other reasons. Adapteva [0] is a startup doing cool things with multi core parallel coprocessors. From their interview on The Amp Hour [1], it seems like their target niche is parallelisable loads that aren't IO constrained, such as computer vision and video processing. Chunks of a video frame don't need to talk to each other. [0]: http://www.adapteva.com/ [1]: http://www.theamphour.com/254-an-interview-with-andreas-olofsson-adate…

I've been fascinated with this machine for ages... I can't believe 20 years have passed so quickly. From time to time I read about R&D projects which remind of it. When Adapteva started talking up their Epiphany Chip & Parallella board, I had hopes that it would be possible to construct a machine which was vaguely reminiscent. That hasn't really come to pass. They've really struggled to get the first generation designs out and they've had to step back from older production schedules. But they haven't completely failed either; you can actually buy boards with 16 core devices now. http://www.adapteva.com/ The Micron Automata Processor Project is also vaguely similar and interesting in its own right. http://www.micron.com/about/innovations/automata-processing

Hopefully the end of cost-effective process shrinks will mean programmers start cleaning up the mess of hugely inefficient everyday software. The party may be winding down for full x86-64 cores, but there's still some room for improvement by increasing efficiency of instructions on those cores and adding new instructions for common tasks (like hashing acceleration instructions, sse9000, etc). Intel already does that with each new processor family. There's a large one-time improvement available for computation-heavy workloads by integrating many simpler high-performance low-power cores into everyday machines (like the epiphany architecture: http://www.adapteva.com/). Intel seems to think only servers will go that route (Xeon Phi), but I don't know about that.

Thanks for posting a very valid concern! Does the following FFT based image processing demo address the concern about communication bottlenecks in the approach? http://www.adapteva.com/white-papers/using-a-scalable-parallel-2d-fft-… Corner turns for 2D FFTs are usually quite challenging for GPUs and CPUs.[ref] Yaniv, our DSP guru, completed the corner turn part of the algorithm with ease in a couple of days and the on chip data movement constitutes a very small portion of the total application wall time.(complete with source code published as well if you really want to dig). It's hard to market FFT cycle counts to the general audience:-)

For an idea in that vein (many 6502's on a die), look at (the sadly defunct) Epiphany, in the Parallela [1] (the buy links are still there but I doubt any are still available). I have two, and they're fun little toys and I wish they'd have gotten further, with the caveat that actually making use of them in a way that'd be better than just resorting to a GPU is hard. The 16-core Epiphany[2] in the Parallella is too small, but they were hoping for 1k or 4k core version. I'm saying it's a similar idea because the Epiphany cores had 32KB on-die RAM per core, and a predictable "single cycle per core traversed" (I think, not checked the docs in years) cost of accessing RAM on the other cores, arranged in a grid. Each core is very simple, though still nowhere near the simplicity of a 6502 (they're 32 bit, w/with a much more "complete" modern instruction set) The challenge is finding a problem that 1) decomposes well enough to benefit from many cores despite low RAM per core (if you need to keep hitting main system memory or neighbouring core RAM, you lose performance fast), 2) does ot decompose well into SIMD style processing where a modern GPU would make mincemeat of it, and 3) is worth the hassle of figuring out how to fit your problem into the memory constraints. I don't know if this is an idea that will ever work - I suspect the problem set where they could potentially compete is too small, but I really wish we'd see more weird hardware attempt like this anyway. [1]…

It would be interesting to throw this URL as far up the internal chain as possible... and see what happens. :P I'm curious myself, and there are a lot of other people who wouldn't mind knowing too. Fast AND trustworthy turnkey silicon is both a completely untapped hole in tech at the moment and something that's desperately needed in this climate of NDA'd garbage-quality security systems (see https://www.devever.net/~hl/smartcards for one of thousands of examples) and increasingly locked down chipsets. I'm not sure what else is out there, but I recently learned of RISC-V (http://www.adapteva.com/andreas-blog/why-i-will-be-using-the-risc-v-in… ); I'll admit I was impressed to learn a free (open design) CPU has just broken the GHz barrier (http://riscv.org/download.html#tab_rocket_core), but this chip and ISA are still in the early prototyping stages, although the spec seems complete. On the other hand, x86 is a widely (!) used, well-known ISA with a lot of legacy software running on it, and VIA already have proven CPUs and chipsets and motherboards. I only know about VIA as "the low-power alternative CPU company," so I have no idea what it's position or stance on secure applications is, but it could well net itself some unique contracts by investing in security. One of the big problems in this space (or at least what's being made into a problem by the major chip vendors) is secure bootstrapping: I can verify the entire boot device (a 128MB boot image could…

Vaguely reminds me of the Adapteva Epiphany RISC multi-processors from the old Parallella Kickstarter project, and presumably others, but that's the one I played with for a while. I'm not sure how this project's interconnect differs, they do say theirs is revolutionary, maybe that's the difference. [1] https://www.adapteva.com/epiphanyiii/ [2] https://parallella.org

This looks really similar to that adapteva chip a few years back.. http://adapteva.com/docs/epiphany_arch_ref.pdf

Adapteva did not use RISC-V. Andreas Olofsson said that, if there was another version, he would probably use RISC-V. [http://www.adapteva.com/andreas-blog/why-i-will-be-using-the-risc-v-in…

I think GPUs, FPGAs and scalar cores will all mix into a single fabric. As you mentioned, FPGAs are getting dedicated hard blocks, GPUs are getting scalar cores and CPUs are getting LUTs. > However, I think an array of ALU's actually could be quite useful for some applications over an FPGA. http://www.adapteva.com/announcements/epiphany-v-a-1024-core-64-bit-ri… http://www.greenarraychips.com/home/documents/greg/PB001-100503-GA144-… http://www.xmos.com/products/silicon/xcore-200

$50M is a very reasonable budget for an AI chip. If they can take advantage of AMD engineers instead of hiring their own they can probably even get away with a smaller budget. http://www.adapteva.com/andreas-blog/semiconductor-economics-101/

Soon we'll have. Google, HP, Oracle Join RISC-V http://www.eetimes.com/document.asp?doc_id=1328561 Adapteva: Why I will be using RISC-V in my next chip http://www.adapteva.com/andreas-blog/why-i-will-be-using-the-risc-v-in…

Did I read the specs wrong or are they claiming a 12x - 15x performance improvement over the Ivy Bridge Xeon in GFLOPS/watt? In a <2w package? http://www.adapteva.com/wp-content/uploads/2013/06/hpec12_olofsson_pub…

Hmm I never heard of the "Parallella". This one has 64 cores but never seems to have been released: http://www.adapteva.com/white-papers/parallella-64-cores/ Is there anything else like that on the market for cheap? I'd actually like to play around with a high core count chip. "Only" 4 cores is for kids :)

100% sure - once you have the masks, pumping out chips is cheap, if you do it in volume. http://www.adapteva.com/andreas-blog/semiconductor-economics-101/

As someone starting a fabless semiconductor startup on less than $2 million, I completely agree with you when it comes to starting a fab (Intel's, GF's, and TSMC's new 14-16nm fabs are in the $10 to $15 billion range), but a fabless semiconductor company can be done for the same range as a software startup. While it is not fair to use my startup as an example (as we don't have silicon in hand just yet), you can look here: http://www.adapteva.com/andreas-blog/semiconductor-economics-101/ http://www.adapteva.com/white-papers/a-lean-fabless-semiconductor-star…

Hi, trsohmers, have you ever heard of Epiphany[1] ? They claim to achieve 70 GFLOPS/WATT. Also the processor seems to be fairly fast and they manage to put 4096 cores on a chip. Though no activity in recent time. Maybe you could find some collaboration points with them.. [1] http://www.adapteva.com/epiphany-multicore-intellectual-property/

Very impressive. How does this compare to other multi-core processors / architectures e.g. epiphany http://www.adapteva.com/introduction/

no, they are very different. NVIDIA is SIMD, a 32 thread warp doing the same instruction in lockstep (in 4 cycles usually on 8 SPs, the 192 SP chip can run 24 warps simultaneously, though specific numbers may change a bit from version to version) and heavily penalized for in-warp divergence. Parallela - i.e. Adapteva (http://www.adapteva.com/epiphanyiv/) is 64 independent (execution-wise) RISC cores.

Epiphany doesn't have any SIMD as far as I can tell. Its honestly 16 (or 64) different CPUs working in a grid. Here's the instruction set for each individual CPU. Each one is small, and weak... but the combination of CPUs makes the architecture very different (and interesting) when compared against the typical SIMT / SIMD GPUs we have today. http://www.adapteva.com/wp-content/uploads/2012/10/epiphany_arch_refer… Its really just 64 (tiny) cores hooked up together. Of course, it can be SIMD if you wanted... (you just hook up all cores to run the same program). But in doing so, it will lose out in comparison to dedicated SIMD engines, like a GPU.

Epiphany Architecture Reference: http://www.adapteva.com/wp-content/uploads/2012/10/epiphany_arch_refer…

Sure thing http://www.adapteva.com/white-papers/building-the-worlds-first-paralle…

Comparing it with a GPU is a natural discussion to have. I believe there is more information on their website to answer the question. But maybe someone else can explain the programming paradigm difference. http://www.adapteva.com/introduction/

Each of the 64 cores can independently run arbitrary C/C++ code, which is much more flexible than a GPU. Each core has 32KB of local memory, which can also be accessed by the other cores, and there's 1GB of external memory too. Specs: http://www.adapteva.com/products/silicon-devices/e64g401/ Architecture: http://www.adapteva.com/wp-content/uploads/2012/10/epiphany_arch_refer… SDK docs: http://www.adapteva.com/wp-content/uploads/2013/04/epiphany_sdk_refere…

I don't really have any comment on the project itself (not something I would ever use and I don't know the value of what they're proposing). But on purely geek terms this thing seems to warrant a "holy shit": http://www.adapteva.com/products/silicon-devices/e64g401/ Again I don't know how (un)common that sort of thing is but I wasn't expecting to see 64 cores in that tiny form factor. Does anyone here know how cutting edge this thing is if at all? [Edit] Also does anyone here want to address use cases for this thing?

Architecture reference manual can be found here: http://www.adapteva.com/support/docs/e3-reference-manual/

http://www.adapteva.com/introduction/ Each core is a RISC processor with local memory. OpenCL is designed to target heterogeneous architectures and map to whatever compute is available.

Seems to be a typo. Looks like this is the correct link: http://www.adapteva.com/products/silicon-devices/.